From 0467faf555022fa5447a037b753b150448217239 Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Wed, 11 Mar 2015 10:34:27 +0100 Subject: Exynos: Clock: Fix exynos5_get_periph_rate for I2C. Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET Cc: Akshay Saraswat Cc: Minkyu Kang Cc: Joonyoung Shim Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c6455c2f3c..2984867290 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -423,8 +423,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: src = EXYNOS_SRC_MPLL; - div = readl(&clk->div_top0); - sub_div = readl(&clk->div_top1); + div = readl(&clk->div_top1); + sub_div = readl(&clk->div_top0); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); -- cgit From f44ef7d60c7349c0eed5d2363a2649badaae2610 Mon Sep 17 00:00:00 2001 From: Inha Song Date: Fri, 13 Mar 2015 17:48:35 +0900 Subject: exynos5: add trace feature #ifdef in exynos5-common.h We can enable / disable trace feature from the FTRACE config options. To enable, compile U-Boot with FTRACE=1. This patch add #ifdef FTRACE in exynos5-common.h for enable/disable to use FTRACE configs instead of having to change board config files. Signed-off-by: Inha Song Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos5-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 3ab8d559bf..2eddb07f0a 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -16,14 +16,14 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL -/* Allow tracing to be enabled */ +#ifdef FTRACE #define CONFIG_TRACE #define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) #define CONFIG_TRACE_EARLY_SIZE (8 << 20) #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000 - +#endif /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA -- cgit From d7e1f02efc8e5272015afed596c395b5a4f8e196 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Thu, 12 Mar 2015 22:33:29 +0100 Subject: config: peach: Correct memory layout environment settings The peach boards have their SDRAM start address at 0x20000000 instead of 0x40000000 which seems common for all other exynos5 based boards. This means the layout set in exynos5-common.h causes the kernel be loaded more then 128MB (at 0x42000000) away from memory start which breaks booting kernels with CONFIG_AUTO_ZRELADDR Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses the same offsets from start of memory as the common exynos5 settings. This fixes booting via bootz and PXE Signed-off-by: Sjoerd Simons Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/peach-pi.h | 8 ++++++++ include/configs/peach-pit.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index f04f0613aa..e3cb09e3d5 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -16,6 +16,14 @@ #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) #define CONFIG_SPI_BOOTING +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + #include #include diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index b5efbdcaa6..3ee42ef2c8 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -16,6 +16,14 @@ #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) #define CONFIG_SPI_BOOTING +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + #include #include -- cgit From 70b4fb660df25d4a150833f7487a0059d1827fee Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:24 +0530 Subject: arm: exynos: add display clocks for Exynos5800 Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock.c | 65 ++++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2984867290..df4d4739ff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -14,7 +14,6 @@ #define PLL_DIV_1024 1024 #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 - /* * * This structure is to store the src bit, div bit and prediv bit * positions of the peripheral clocks of the src and div registers @@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; } +static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * CLKMUX_FIMD1 [6:4] + */ + sel = (readl(&clk->src_disp10) >> 4) & 0x7; + + if (sel) { + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, + RPLL}; + sclk = get_pll_clk(reg_map[sel]); + } else + sclk = CONFIG_SYS_CLK_FREQ; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); } +void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (0x7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1660,8 +1717,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 2a17dfc6de..d20b7d2ae3 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4)) -- cgit From 6102560891d09db79196654aa414afc5acfa7911 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:25 +0530 Subject: Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0d0c..0200fd154f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, -- cgit From 9018efa7e227bc7041a98f5c5efebaa7ecfcfd0d Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:26 +0530 Subject: video: exynos_fb: configure backlight GPIOs if specified in DT Add support to configure PWM_OUT(PWM output) GPIO and BL_EN(backlight enable) GPIO, if provided in FIMD DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- doc/device-tree-bindings/video/exynos-fb.txt | 2 ++ drivers/video/exynos_fb.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index dc4e44fbc5..b022f6163f 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -61,6 +61,8 @@ Board(panel specific): disabled with compatible string "samsung,sysmmu-v3.3", with a "reg" property holding the register address of FIMD sysmmu. + samsung,pwm-out-gpio: PWM output GPIO. + samsung,bl-en-gpio: backlight enable GPIO. Example: SOC specific part: diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index c5d7330804..8f3b8263da 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "exynos_fb.h" @@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid) static void lcd_panel_on(vidinfo_t *vid) { + struct gpio_desc pwm_out_gpio; + struct gpio_desc bl_en_gpio; + unsigned int node; + udelay(vid->init_delay); exynos_backlight_reset(); @@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid) exynos_backlight_on(1); +#ifdef CONFIG_OF_CONTROL + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) { + debug("FIMD: Can't get device node for FIMD\n"); + return; + } + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio", + 0, &pwm_out_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0, + &bl_en_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + +#endif exynos_cfg_ldo(); exynos_enable_ldo(1); -- cgit From 55e70929b83bc512721d08cb32a7523458d9122d Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:27 +0530 Subject: video: parade: configure SLP and RST GPIOs if specified in DT Add support to configure EDP_RST GPIO and EDP_SLP GPIO, if provided in parade DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/video/parade.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/parade.c b/drivers/video/parade.c index 0f543f653c..ae5097160f 100644 --- a/drivers/video/parade.c +++ b/drivers/video/parade.c @@ -12,6 +12,7 @@ #include #include #include +#include /* * Initialization of the chip is a process of writing certaing values into @@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table) int parade_init(const void *blob) { + struct gpio_desc rst_gpio; + struct gpio_desc slp_gpio; int bus, old_bus; int parent; int node; @@ -201,6 +204,14 @@ int parade_init(const void *blob) return -1; } + gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + mdelay(10); + + gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + bus = i2c_get_bus_num_fdt(parent); old_bus = i2c_get_bus_num(); -- cgit From e549234d698406099e8bbeda4a345d8c77250cf1 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:28 +0530 Subject: dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node Now that the exynos_fb driver supports handling backlight GPIO via DT, specify pwm output property via FIMD DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos54xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 916cf3a5b6..31fabb190e 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -168,6 +168,7 @@ fimd@14400000 { /* sysmmu is not used in U-Boot */ samsung,disable-sysmmu; + samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>; }; dp@145b0000 { -- cgit From b798177736f006125b4769986f232e4b0a4f9a84 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:29 +0530 Subject: dts: peach_pit: Add SLP and RST GPIO properties in parade DT node Now that parade driver supports reading SLP and RST GPIO from DT, specify the same in parade DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5420-peach-pit.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index b801de9787..3ad4728138 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -67,6 +67,8 @@ edp-lvds-bridge@48 { compatible = "parade,ps8625"; reg = <0x48>; + sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>; }; }; -- cgit From 607eff62ce99da2a528be1678b0bade67df01cc1 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:30 +0530 Subject: dts: peach_pi: Add DT properties needed for display Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5800-peach-pi.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100995..494f7641e7 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,10 +144,13 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <30000>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; samsung,dual-lcd-enabled = <0>; + + samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>; }; }; -- cgit From 0f00c38f017feb7f7e710b320e22560d1bd4add7 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Wed, 4 Mar 2015 19:05:31 +0530 Subject: smdk5420: Remove GPIO enums Remove GPIOs from smdk5420 board file and because the same is already specified via DT. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- board/samsung/smdk5420/smdk5420.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 1aca9fabd9..82f607b24d 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -58,16 +58,6 @@ void exynos_lcd_power_on(void) mdelay(5); - /* TODO(ajaykumar.rs@samsung.com): Use device tree */ - gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); - gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ - mdelay(10); - gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); - gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ - gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); - gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ - gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); - if (has_edp_bridge()) if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__); @@ -75,11 +65,6 @@ void exynos_lcd_power_on(void) void exynos_backlight_on(unsigned int onoff) { - /* For PWM */ - gpio_request(EXYNOS5420_GPIO_B20, "backlight_on"); - gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1)); - gpio_set_value(EXYNOS5420_GPIO_B20, 1); - #ifdef CONFIG_POWER_TPS65090 tps65090_fet_enable(1); #endif -- cgit From f26cc7d4edc2f6d5adb35e8e4ce8ae0549e09f8f Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Wed, 1 Apr 2015 12:34:28 +0200 Subject: config: exynos: common: Provide env variables to support Image.itb This change allows using Image.itb image format with Exynos4 devices (especially trats and trats2). Such change facilitates automated testing since only one binary needs to be prepared. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/exynos4-common.h | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 41631c72e9..577afe7e8f 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -66,4 +66,58 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE +/* Common environment variables */ +#define CONFIG_EXTRA_ENV_ITB \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \ + " ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${board_name}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" + #endif /* __CONFIG_EXYNOS4_COMMON_H */ -- cgit From 0a1387bf1b8beaa336b6e8991520904ff6f2dc98 Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Wed, 1 Apr 2015 12:34:29 +0200 Subject: config: exynos: trats: Enable support for Image.itb at trats device After this change it is possible to boot trats device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/trats.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/trats.h b/include/configs/trats.h index b21ea2de5f..6808e789f3 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -51,8 +51,10 @@ #define MACH_TYPE_TRATS 3928 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -106,7 +108,8 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8\0" + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ @@ -172,6 +175,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ -- cgit From 1018b0a56a4719a64fb6867337a72d6a9343008b Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Wed, 1 Apr 2015 12:34:30 +0200 Subject: config: exynos: trats2: Enable support for Image.itb at trats2 device After this change it is possible to boot trats2 device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/trats2.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 42481ab6e1..94c31fbf2b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -44,8 +44,10 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -96,7 +98,8 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8\0" + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ @@ -153,6 +156,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ "fdtaddr=40800000\0" \ /* GPT */ -- cgit