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* | gpio: sandbox: Use a separate flag for the valueSimon Glass2021-03-031-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present with the sandbox GPIO driver it is not possible to change the value of GPIOD_IS_OUT_ACTIVE unless the GPIO is an output. This makes it hard to test changing the flags since we need to be aware of the internal workings of the driver. The feature is designed to aid testing. Split this feature out into a separate sandbox-specific flag, so that the flags can change unimpeded. This will make it easier to allow updating the flags in a future patch. Signed-off-by: Simon Glass <sjg@chromium.org>
* | gpio: sandbox: Rename GPIO dir_flags to flagsSimon Glass2021-03-031-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | Adjust the terminology in this driver to reflect that fact that all flags are handled, not just direction flags. Create a new access function to get the full GPIO state, not just the direction flags. Drop the static invalid_dir_flags since we can rely on a segfault if something is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | gpio: Rename dm_gpio_get_dir_flags() to dm_gpio_get_flags()Simon Glass2021-03-031-1/+1
| | | | | | | | | | | | | | | | | | This function can be used to get any flags, not just direction flags. Rename it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
* | dm: gpio: Rename get_dir_flags() method to get_flags()Simon Glass2021-03-034-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is more useful to be able to read all the flags, not just the direction ones. In fact this is what the STM32 driver does. Update the method name to reflect this. Tweak the docs a little and use 'flagsp' as the return argument, as is common in driver model, to indicate it returns a value. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
* | dm: gpio: Rename set_dir_flags() method to update_flags()Simon Glass2021-03-034-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | The current method is a misnomer since it is also used (e.g. by stm32) to update pull settings and open source/open drain. Rename it and expand the documentation to cover a few more details. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | gpio: Disable functions not used with of-platdataSimon Glass2021-03-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions use devicetree and cannot work with of-platdata, which has no runtime devicetree. If they are used, the current linker error is confusing, since it talks about missing functions in the bowels of driver model. Avoid compiling these functions at all with of-platdata, so that a straightforward link error points to the problem. Series-changes; 3 - Fix 'wprl' typo Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | tpm: Use logging in the uclassSimon Glass2021-03-021-3/+5
| | | | | | | | | | | | | | Update this to use log_debug() instead of the old debug(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | tpm: Don't include cr50 in TPL/SPLSimon Glass2021-03-022-3/+3
| | | | | | | | | | | | | | | | | | | | At present the security chip is not used in these U-Boot phases. Update the Makefile to exclude it. Fix a few logging statements while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-023-3/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini2021-02-266-100/+255
|\ | | | | | | - fastboot updates / fixes
| * usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and ↵Patrice Chotard2021-02-261-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_gadget_register_driver() Since commit 8745b9ebccae ("usb: gadget: add super speed support") ums was no more functional on platform which use dwc2_udc_otg driver. This was due to a too restrictive test which checked that the gadget driver speed was either FS or HS. So all gadget driver with max speed set to speed higher than HS (SS in case of composite gadget driver in our case) are not allowed, which is wrong. Update the speed test in usb_gadget_register_driver() and in dwc2_gadget_start() to allow all gadget driver speed equal or higher than FS. Tested on stm32mp157c-ev1 board. Fixes: c791c8431c34 ("usb: dwc2: convert driver to DM_USB_GADGET") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * fastboot: add UUU command UCmd and ACmd supportHeiko Schocher2021-02-263-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the UUU commands ACmd and UCmd. Enable them through the Kconfig option CONFIG_FASTBOOT_UUU_SUPPORT base was commit in NXP kernel 9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support") and ported it to current mainline. Tested this patch on imx6ul based board. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * fastboot: Allow u-boot-style partitionsSean Anderson2021-02-261-59/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for partitions of the form "dev.hwpart:part" and "dev#partname". This allows one to flash to eMMC boot partitions without having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME. Lastly, one can also flash MMC devices other than CONFIG_FASTBOOT_FLASH_MMC_DEV. Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV is used only when necessary for existing functionality. For those cases, fastboot_mmc_get_dev has been added as a helper function. This allows There should be no conflicts with the existing system, but just in case, I have ordered detection of these names after all existing names. The fastboot_mmc_part test has been updated for these new names. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_nameSean Anderson2021-02-261-22/+22
| | | | | | | | | | | | | | This makes the next commit more readable by doing the move now. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fastboot: Remove mmcpart argument from raw_part_get_info_by_nameSean Anderson2021-02-261-23/+18
| | | | | | | | | | | | | | | | | | | | The only thing mmcpart was used for was to pass to blk_dselect_hwpart. This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The error handling is dropped, but it is reintroduced in the next commit (albeit less specificly). Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mmc: sandbox: Add support for writingSean Anderson2021-02-261-6/+37
| | | | | | | | | | | | | | | | | | | | This adds support writing to the sandbox mmc backed by an in-memory buffer. The unit test has been updated to test reading, writing, and erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF then that can be easily changed. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini2021-02-264-14/+84
|\ \ | | | | | | | | | | | | - new GigaDevice flash ids - fixes for imx, nxp_spi drivers
| * | mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxGReto Schneider2021-02-261-10/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relevant changes to the already existing GD5F1GQ4UExxG support has been determined by consulting the GigaDevice product change notice AN-0392-10, version 1.0 from November 30, 2020. As the overlaps are huge, variable names have been generalized accordingly. Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes), the new device ID, and the extra quad IO dummy byte, no changes had to be taken into account. New hardware features are not supported, namely: - Power on reset - Unique ID - Double transfer rate (DTR) - Parameter page - Random data quad IO The inverted semantic of the "driver strength" register bits, defaulting to 100% instead of 50% for the Q5 devices, got ignored as the driver has never touched them anyway. The no longer supported "read from cache during block erase" functionality is not reflected as the current SPI NAND core does not support it anyway. Implementation has been tested on MediaTek MT7688 based GARDENA smart Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG. Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: nand: spi: Only one dummy byte in QUADIOHauke Mehrtens2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The datasheet only lists one dummy byte in the 0xEB operation for the following chips: * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG Reto Schneider: - Linux patch ported to U-Boot - Checked for compatibility with GD5F1GQ4xBxxG - Fixed operation code in original commit message (0xEH -> 0xEB) Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: nxp_fspi: Fix error reportingAdam Ford2021-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-ids: Add support of flash protection to w25q128Su Baocheng2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents various models. From Winbond's website, I could only find 3 types of them: W25Q128JV-IQ/JQ datasheet:https://www.winbond.com/resource-files/ w25q128jv%20revg%2004082019%20plus.pdf W25Q128FV (SPI Mode) datasheet: https://www.winbond.com/resource-files/ w25q128fv%20rev.m%2005132016%20kms.pdf W25Q128BV datesheet: https://www.winbond.com/resource-files/ w25q128bv_revh_100313_wo_automotive.pdf According to the datasheets, all of these 3 types support BP(0,1,2) and TB bits in the status register (SR), so it could reuse the flash protection logic for ST Micro. So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB flags to the w25q128 entry of spi_nor_ids table. Signed-off-by: Su Baocheng <baocheng.su@siemens.com> [jagan: remove comments in spi-nor-ids.c] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-ids: Add Gigadevice GD25LQ64CAlper Nebi Yasak2021-02-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on rk3399-gru-kevin: => sf probe SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB => sf erase 0x600000 0x200000 SF: 2097152 bytes @ 0x600000 Erased: OK => sf test 0x700000 0x1000 SPI flash test: 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps Test passed 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps The values are the same as in Linux, except adjusted for the U-Boot definition of INFO(). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: imx: Implement set_speedMarek Vasut2021-02-261-1/+4
| |/ | | | | | | | | | | | | | | | | The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-02-2613-48/+112
|\ \ | | | | | | | | | | | | | | | | | | | | | - turris_mox: Enhancements, mostlly defconfig changes (Pali) - pci-aardvark: Set Max Payload Size and Max Read Request Size to 512 bytes (Pali) - pci_mvebu: Minor cleanup and refactoring (Marek) - Upgrade A38x DDR3 training to version 14.0.0 (Marek)
| * | ddr: marvell: a38x: fix comment in conditional macroMarek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was processed with unifdef utility to omit portions not relevant to A38x and DDR3. This removes usage of many macros, including A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove the macros from #else comment. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: bump version to 14.0.0Marek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the version in the mv-ddr-devel branch of upstream repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. There is a new version numbering system, where after 18.12.0 came 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: enum mv_ddr_twin_die: change orderheaterC2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream. @pali suggested this change In commit 6285efb ("mv_ddr: add support for twin-die combined memory device") was added support for twin-die combined memory device and default value for explicitly uninitialized structure members is zero, s also twin_die_combined is initialized to zero. Which means COMBINED value. As prior this commit there was no support for twin-die combined memory device, default value for twin_die_combined should be NOT_COMBINED. This change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED has value zero. Signed-off-by: heaterC <airyguy@gmx.de> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import code change from upstreamMarek Behún2021-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes code in ddr3_training.c. Import this change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix memory cs size functionMoti Buskila2021-02-262-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream. The funtion returnd cs size in byte instead of MB, that cause calculation error since the caller was expected to get u32 and when he got above 4G it refers it as 0. The fix was to get the cs memory size from function as in MB and then multiply it by 1MB. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bitMoti Buskila2021-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream. WL phase correcion stage is failing while using bus_width of 16bit, not to be fix this stage is un-necessary when working with bus_width of 16 bit. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add support for twin-die combined memory deviceMoti Buskila2021-02-262-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream. the twin-die combined memory device should be treatened as X8 device and not as X16 one Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> [ - the default value for twin_die_combined is set to NOT_COMBINED for all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add 16Gbit memory devices supportMoti Buskila2021-02-262-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: allow board specific ODT configurationBaruch Siach2021-02-262-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream. The ODT enable heuristic based on active chip-selects is not always correct. Some board might use two chip-selects, but have only one ODT line connected. Allow board specific mv_ddr_topology_map to directly set the ODT configuration register value. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Moti Buskila <motib@marvell.com> Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix memory size calculation using 32bit bus widthMoti Buskila2021-02-263-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ab9240402a70cc02496683971779e75eff410ab4 upstream. - function mv_ddr_spd_die_capacity_user_get() has a bug, since it insert a user memory enum to it, instead of SPD memory enum (which are different) - fix: remove mv_ddr_spd_die_capacity_user_get() function. - memory size with 64 and 32 bit already calculated correctly at mv_ddr_mem_sz_per_cs_get() function Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com> Reviewed-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix 32bitMoti Buskila2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header mv_ddr_topology.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add ddr 32bit ECC supportAlex Leibovich2021-02-263-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add ddr32 supportAlex Leibovich2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a165037ec26f301be75e1fabc263643683e85255 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix write leveling suplementary algoMoti Buskila2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ce62bef8fac559e27245259882e45f19cdc293ad upstream. - fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | pci: pci_mvebu: set local dev to number 1Marek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: refactor validation of addresses for config accessMarek Behún2021-02-261-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: debug rd/wr config as other drivers doMarek Behún2021-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: cosmetic fixMarek Behún2021-02-261-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: use dev_seq instead of static variableMarek Behún2021-02-261-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytesPali Rohár2021-02-261-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini2021-02-265-142/+8
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| * serial: s5p: Allow independent selectionMark Kettenis2021-02-232-1/+8
| | | | | | | | | | | | | | | | | | | | | | Currently support for the Samsung serial port driver is part of CONFIG_S5P which controls selection of several drivers for the S5P family. Give it its own config option such that we can use it on other SoCs as well. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit (git 2.34.1) at 2025-09-29 06:06:13 +0000