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| * | ata: DWC_AHSATA depends on BLKTom Rini2021-04-101-0/+1
| | | | | | | | | | | | | | | | | | | | | The dwc ahsata driver is written such that CONFIG_BLK must be enabled, add this as a dependency in Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge tag 'video-2021-07-rc1' of ↵Tom Rini2021-04-1113-52/+303
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-video - rk3399 eDP support - pwm backlight without a known period_ns - add Chrome OS EC PWM driver - Kconfig SIMPLE_PANEL DM_GPIO dependency - remove mb862xx driver remnants - fix KiB format in reserve_video() debug trace - fix tegra124 sor CSTM LVDS_EN_ENABLE/DISABLE config - fix line padding calculation for 16 and 24 BPP bitmaps
| * | video: Fix line padding calculation for 16 and 24 BPP bitmapsSylwester Nawrocki2021-04-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each row in the pixel array in the bitmap file is padded if necessary so the row size is always a multiple of 4 bytes. In current code the complement of row size to a multiple of 4 bytes is further unnecessarily multiplied by the pixel size. This results in incorrect displaying of bitmaps having row size that is not a multiple of 4 bytes. Fix this by removing the unnecessary multiplication. Tested with 24BPP bitmap and XRGB32 display. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | tegra: video: fix tegra_dc_sor_config_panel()Heinrich Schuchardt2021-04-101-2/+2
| | | | | | | | | | | | | | | | | | | | | Bitwise OR has a higher operator precedence than the ternary conditional. Add the missing parentheses. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | finish removing mb862xx video driverTrevor Woerner2021-04-101-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | drivers/video/mb862xx.c was removed in commit 9c1e098fb92de38f0017585658dd50c3009c84ab from December 2020, however, this last little remnant in drivers/video/cfb_console.c remained. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
| * | video: SIMPLE_PANEL depends on DM_GPIOAsherah Connor2021-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SIMPLE_PANEL currently only depends on PANEL && BACKLIGHT, but the code makes references to dm_gpio_set_value and gpio_request_by_name. These are defined in drivers/gpio/gpio-uclass.c, so a dependency on DM_GPIO corrects these link errors: aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_set_backlight': /home/kameliya/u-boot/drivers/video/simple_panel.c:42: undefined reference to `dm_gpio_set_value' aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_enable_backlight': /home/kameliya/u-boot/drivers/video/simple_panel.c:27: undefined reference to `dm_gpio_set_value' aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_of_to_plat': /home/kameliya/u-boot/drivers/video/simple_panel.c:72: undefined reference to `gpio_request_by_name' This issue is only exposed if you have a board which enables CONFIG_DM_VIDEO without CONFIG_DM_GPIO; so far, none do, but soon a QEMU board may. Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
| * | pwm: Add a driver for Chrome OS EC PWMAlper Nebi Yasak2021-04-104-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PWM is used in rk3399-gru-bob and rk3399-gru-kevin to control the display brightness. We can only change the duty cycle, so on set_config() we just try to match the duty cycle that dividing duty_ns by period_ns gives us. To disable, we set the duty cycle to zero while keeping the old value for when we want to re-enable it. The cros_ec_set_pwm_duty() function is taken from Depthcharge's cros_ec_set_bl_pwm_duty() but modified to use the generic pwm type. The driver itself is very loosely based on rk_pwm.c for the general pwm driver structure. The devicetree binding file is from Linux, before it was converted to YAML at 5df5a577a6b4 ("dt-bindings: pwm: Convert google,cros-ec-pwm.txt to YAML format") in their repo. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | video: backlight: Support PWMs without a known period_nsAlper Nebi Yasak2021-04-102-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PWM device provided by Chrome OS EC doesn't really support anything other than setting a relative duty cycle. To support it as a backlight, this patch makes the PWM period optional in the device tree and pretends the valid brightness range is its period_ns. Also adds a sandbox test for a PWM channel that has a fixed period, checking that the resulting duty_cycle matches on a set_config() even if the requested period_ns can't be set. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: video: vop: Add reset supportArnaud Patard (Rtp)2021-04-101-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that the VOP registers are in correct state, add missing support for the VOP reset lines found in the device-tree Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | rockchip: video: edp: Add missing reset supportArnaud Patard (Rtp)2021-04-101-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that the eDP registers are in correct state, add missing support for the eDP reset lines found in the device-tree. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | rockchip: video: vop: Fix format of fbbase in debug stringArnaud Patard (Rtp)2021-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The debug string printing the device name, framebuffer address and of node is using %lu as format for the framebuffer address, which is not so nice. Change it to %lx. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | rockchip: pwm: Fix default polarityArnaud Patard (Rtp)2021-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the code, the default polarity is set to positive/positive, which is neither normal polarity or inverted polarity. It's only the hardware default. This leads to booting linux with wrong polarity setting. Update the code to use PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE by default instead. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | Rockchip: video: vop: Reserve efi fb memoryArnaud Patard (Rtp)2021-04-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | When booting with EFI and graphics, the memory used for framebuffer has to be reserved, otherwise it may leads to kernel memory overwrite. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | rockchip: video: edp: Add rk3399 supportArnaud Patard (Rtp)2021-04-101-20/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to linux commit "drm/rockchip: analogix_dp: add rk3399 eDP support" (82872e42bb1501dd9e60ca430f4bae45a469aa64), rk3288 and rk3399 eDP IPs are nearly the same, the difference is in the grf register (SOC_CON6 versus SOC_CON20). So, change the code to use the right register on each IP. The clocks don't seem to be the same, the eDP clock is not at index 1 on rk3399, so don't try changing the clock at index 1 to rate 0 on rk3399. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | rockchip: video: vop: Use endpoint compatible string to find VOP modeArnaud Patard (Rtp)2021-04-101-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code is using an hard coded enum and the of node reg value of endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order is different between rk3288, rk3399 vop little, rk3399 vop big. A possible solution would be to make sure that the rk3288.dtsi and rk3399.dtsi files have "expected" reg value or an other solution is to find the kind of endpoint by comparing the endpoint compatible value. This patch is implementing the more flexible second solution. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
* | | Merge tag 'u-boot-stm32-20210409' of ↵Tom Rini2021-04-091-0/+3
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm Add rt-thread art-pi board support based on STM32H750 SoC Add Engicam i.Core STM32MP1 SoM Add FIP header support for STM32programmer Update uart number when no serial device found for STM32MP1 Remove board_check_usb_power function when ADC flag is not set Update SPL size limitation for STM32MP1 Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
| * | ram: stm32: fix strsep failed on read only memorydillon min2021-04-091-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | strsep will change data from original memory address, in case the memory is in non-sdram/sram place, will run into a bug(hang at SDRAM: ) just add a temporary array to store bank_name[] to fix this bug. Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | Merge tag 'u-boot-imx-20210409' of ↵Tom Rini2021-04-0916-99/+325
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210409 ------------------- - Secure Boot : - HAB for MX8M / MX7ULP - CAAM fixes - Fixes for imxrt1020 - Fixes for USDHC driver - Fixes for Toradex (Colibri / Apalis) - Switch to DM for several boards - mx23 olinuxo - usbarmory - marsboard / riotboard - Gateworks GW Ventana - NXP upstream patches (LPDDR / CAAM / HAB) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
| * | mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessaryHaibo Chen2021-04-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need around 18ms, common code only delay 10ms, so need to delay extra 8ms. Otherwise voltage switch will timeout when wait for data0 line. This IO voltage switch time depends on board design, depend on the PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF capacitance. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | mmc: fsl_esdhc_imx: remove redundant cmd11 related code.Haibo Chen2021-04-081-9/+0
| | | | | | | | | | | | | | | | | | | | | Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock outputHaibo Chen2021-04-081-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | spl: fit: nand: allow for non-page-aligned elementsTim Harvey2021-04-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a weak nand_get_mtd function for nand drivers to provide mtd info and use this to set pagesize such that reading of non page-aligned elements can succeed. The spl_load_simple_fit already handles block block access so all we need to do is provide the nand writesize as the block length. Further cleanup of the drivers which use nand_spl_loaders.c such as am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done using info from mtd_info instead of statically defined details. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | crypto: fsl: refactor for 32 bit version CAAM support on ARM64Ye Li2021-04-088-72/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | fsl_mfgprot: Fix typo in sign_mppubk()Breno Lima2021-04-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The signature is generated using manufacturing protection private key. Fix typo in fsl_mfgprot.c. Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | imx8m: Add DEK blob encapsulation for imx8mClement Faure2021-04-081-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DEK blob encapsulation support for IMX8M through "dek_blob" command. On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob for encrypted boot. The DEK blob is encapsulated by OP-TEE through a trusted application call. U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE dynamic shared memory. To enable the DEK blob encapsulation, add to the defconfig: CONFIG_SECURE_BOOT=y CONFIG_FAT_WRITE=y CONFIG_CMD_DEKBLOB=y Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | crypto: caam: Fix pointer size to 32bit for i.MX8MAymen Sghaier2021-04-085-32/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CAAM block used in i.MX8M is 32 bits address size but when the flag PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a wrong pointer size. This patch fixes this issue. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | crypto: caam: Fix build warnings pointer castingAymen Sghaier2021-04-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture, lead to casting warnings: from/to pointer to/from integer with different size. This patch fix these warnings Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | crypto: caam: Add CAAM support to i.MX8M platformsAymen Sghaier2021-04-081-1/+3
| | | | | | | | | | | | | | | | | | | | | This patch enable CAAM support for i.MX8M platforms. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | caam: enable support for iMX7ULPFranck LENORMAND2021-04-081-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | crypto: caam: change JR running loopFranck LENORMAND2021-04-082-7/+9
| | | | | | | | | | | | | | | Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | crypto: fsl: blob: Flush dcache range for destination addressBreno Lima2021-04-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM devices. Due to different cache management it's necessary to flush dcache range for destination address so data can be available in memory. Add necessary operations in blob_encap() and blob_decap() functions. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | imx: imx7 Support for Manufacturing ProtectionBreno Lima2021-04-083-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code was originally developed by Raul Cardenas <raul.casas@nxp.com> and modified to be applied in U-Boot imx_v2017.03. More information about the initial submission can be seen in the link below: https://lists.denx.de/pipermail/u-boot/2016-February/245273.html i.MX7D has an a protection feature for Manufacturing process. This feature uses asymmetric encryption to sign and verify authenticated software handled between parties. This command enables the use of such feature. The private key is unique and generated once per device. And it is stored in secure memory and only accessible by CAAM. Therefore, the public key generation and signature functions are the only functions available for the user. The manufacturing-protection authentication process can be used to authenticate the chip to the OEM's server. Command usage: Print the public key for the device. - mfgprot pubk Generates Signature over given data. - mfgprot sign <data_address> <data_size> Signed-off-by: Raul Ulises Cardenas <raul.casas@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | misc: ocotp: Update OCOTP driver for iMX8MQ B2Ye Li2021-04-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register, so it does not support "fuse sense" command like B1. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | power: pca9450: add a new parameter for power_pca9450_initPeng Fan2021-04-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Currently PCA9450 might have address 0x25 or 0x35, so let user choose the address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | imx8mp: refine power on imx8mp boardhaidong.zheng2021-04-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-04-085-15/+28
|\ \ \ | | | | | | | | | | | | - Watchdog, Unleashed and Icicle improvements
| * | | clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flagBin Meng2021-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
| * | | timer: sifive_clint: Support the official clint DT bindingsBin Meng2021-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * | | riscv: sifive: Rename fu540 board to unleashedBin Meng2021-04-082-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * | | wdt: dw: Free the clock on errorSean Anderson2021-04-081-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock subsystem requires that clk_free be called on clocks obtained via clk_get_*. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | wdt: dw: Enable the clock before using itSean Anderson2021-04-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog won't work if the clock isn't enabled. Fixes: cf89ef8d10f240554541c20b2e1bdcdd58d1d7e6 Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | wdt: dw: Switch to if(CONFIG()) instead of using #ifSean Anderson2021-04-081-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is preferred over #if because the compiler can check syntax even if the feature is disabled. This cannot be used for CONFIG_CLK because CONFIG_DW_WDT_CLOCK_KHZ is not defined on all platforms. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | | wdt: dw: Switch to using fls for log2Sean Anderson2021-04-081-2/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | log_2_n_round_up is only found in arm. fls performs the same job and is generic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: mvebu: convert to driver modelHarm Berntsen2021-04-082-126/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a straightforward conversion of the old, non-dm driver. It was done in-place as the deadline for non-dm MMC has passed. Previous commits ensured that no board depends on the old, non-dm variant. Tested on a Kirkwood based board with eMMC. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> Tested-by: Harm Berntsen <harm.berntsen@nedap.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> CC: Pantelis Antoniou <panto@antoniou-consulting.com> CC: Stefan Roese <sr@denx.de> CC: Gerald Kerma <drEagle@doukki.net> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | rtc: add armada38x driverMarek Behún2021-04-083-0/+192
|/ / | | | | | | | | | | | | | | | | | | | | | | | | Add RTC driver for Armada 38x, based on Linux' driver. For now implement only `marvell,armada-380-rtc` compatible. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Chris Packham <judge.packham@gmail.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Pali Rohár <pali@kernel.org>
* | Merge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini2021-04-064-12/+45
|\ \ | | | | | | | | | | | | | | | | | | | | | Update hwpartition usage Check bootbus's arguments workaround for erratum A-011334 for fsl_esdhc driver add pulse width detection workaround for fsl_esdhc driver Use alias num before checking mmc index when creating device
| * | mmc: mmc-uclass: Use dev_seq() to read aliases node's indexAswath Govindraju2021-04-061-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use dev_seq() to read aliases node's index and pass it as device number for creating bulk device. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: Check for device with a seq number equal to num before checking against ↵Aswath Govindraju2021-04-061-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | index First check if there is an alias for the device tree node defined with the given num before checking against device index. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: fsl_esdhc: add pulse width detection workaroundMichael Walle2021-04-062-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: fsl_esdhc: add workaround for erratum A-011334Michael Walle2021-04-062-1/+27
| | | | | | | | | | | | | | | | | | | | | LS1028A SoCs are restricted in what divider values are allowed for HS400 mode. This is basically a port from the corresponding linux driver. Signed-off-by: Michael Walle <michael@walle.cc>