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* | | video: sunxi: Use DW-HDMI hpd functionJernej Skrabec2021-04-241-28/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that there are two ways how hot plug detection can be done. One is standard way for DW HDMI controller - checking bit 2 in 0x3004 register. Another way is applicable only to Allwinner custom PHY - by checking bit 19 in register 0x10038. Both methods are equally good as far as we know. Use standard method in order to reduce amount of custom code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | video: sunxi: Add mode_valid callback to sunxi_dw_hdmiJernej Skrabec2021-04-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently driver accepts all resolution which won't work on 4k screens. Add validation callback which limits acceptable resolutions to 297 MHz. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini2021-04-232-0/+28
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| * | usb: ehci-hcd: Add IAA handshake for removing async QHYe Li2021-04-222-0/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to EHCI spec, software needs to do handshake with HC for safely removing QH from async list. This handshake is implemented by setting IAAD (Interrupt on Async Advance Doorbell) bit in USB_USBCMD register and poll the IAA (Interrupt on Async Advance bit) in the USB_USBSTS to ensure the HC has released all on-chip state that may potentially reference one of the data structures just removed. Current codes only check active status of the last QTD, but this can't ensure the QH is released from HC. We can meet unrecoverable "EHCI timed out on TD" errors when running UEFI SCT tests on USB disk. The USB_ASYNCLISTADDR register is changed to a invalid address when the issue happens. It is fixed after adding the IAA handshake. Steps to reproduce the issue: 1. Build the UEFI SCT from https://github.com/tianocore/edk2-test 2. Build the EDK2 UEFI Shell from https://github.com/tianocore/edk2 3. Copy SCT files and Shell.efi to USB disk FAT partition 4. Load the Shell.efi from USB FAT, and run bootefi to execute it 5. After booting into Shell, enter the SCT directory and run "sct -a" to execute all tests. 6. Tests run about 1 hour and stop with many EHCI timeout errors like EHCI timed out on TD - token=0x801f8c80 Signed-off-by: Ye Li <ye.li@nxp.com>
* | mmc: octeontx_hsmmc: Add support for MIPS OcteonStefan Roese2021-04-222-56/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the Octeontx MMC driver did only support the ARM Octeon TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform to this driver. Here a short summary of the changes: - Enable driver compilation for MIPS Octeon, including the MMC related header file - Reorder header inclusion - Switch to using the clk framework to get the input clock - Remove some functions for MIPS Octeon, as some registers don't exist here Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | net: jr2: Fix Serdes6G configurationHoratiu Vultur2021-04-221-4/+23
| | | | | | | | | | | | | | | | | | | | Sometimes no traffic was getting out on the ports, the root cause was a wrong configuration of the Serdes6G, which is used on jr2 pcb111. This patch fixes this issue by applying the correct configuration. Fixes: 5e1d417bec92ac ("net: Add MSCC Jaguar2 network driver.") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: jr2: Reset switchHoratiu Vultur2021-04-221-1/+15
|/ | | | | | | Make sure to reset the switch core at probe time. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* sysreset: provide type of reset in do_reset cmdIgor Opaniuk2021-04-201-1/+10
| | | | | | Add additional param for reset cmd, which provides type of reset. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
* sysreset: psci: use psci driver exported functionsIgor Opaniuk2021-04-201-6/+2
| | | | | | | Use psci driver exported functions for reset/poweroff, instead of invoking directly invoke_psci_fn. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
* psci: add features/reset2 supportIgor Opaniuk2021-04-201-0/+68
| | | | | | | | | | | | | | | | | | | | Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
* net: calxedagmac: Convert to DM_ETHAndre Przywara2021-04-202-64/+135
| | | | | | | | | | | | | | | | | | To squash that nasty warning message and make better use of the newly gained OF_CONTROL feature, let's convert the calxedagmac driver to the "new" driver model. The conversion is pretty straight forward, mostly just adjusting the use of the involved data structures. The only actual change is the required split of the receive routine into a receive and free_pkt part. Also this allows us to get rid of the hardcoded platform information and explicit init calls. This also uses the opportunity to wrap the code decoding the MMIO register base address, to make it safe for using PHYS_64BIT later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* power: regulator: add driver for ANATOP regulatorYing-Chun Liu (PaulLiu)2021-04-203-0/+289
| | | | | | | | | | | | | | Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* net: octeontx: smi: fix mii probeTim Harvey2021-04-201-0/+2
| | | | | | | | | The fdt node offset is apparently not set properly when probed causing no MDIO busses to be found. Fix this by obtaining the offset. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: ata: ahci: update max id if it is more than available portsSuneel Garapati2021-04-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After check for maximum between max id and available ports, also check if available port count is less than max id and update. In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to the number of ports found otherwise the following occurs on a scan: GW6404-B> scsi scan scanning bus for devices... Target spinup took 0 ms. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233 Type: Hard Disk Capacity: 61057.3 MB = 59.6 GB (125045424 x 512) "Synchronous Abort" handler, esr 0x96000006 elr: 000000000052f824 lr : 000000000052fa10 (reloc) elr: 000000007fee9824 lr : 000000007fee9a10 x0 : 0000000000000001 x1 : 0000000000000001 x2 : 000000007bea3528 x3 : 000000007bea3580 x4 : 0000000000000200 x5 : 0000000000000000 x6 : 0000000000000002 x7 : 000000007bea3540 x8 : 00000000fffffff8 x9 : 0000000000000008 x10: 00000000000186a0 x11: 000000000000000d x12: 0000000000000006 x13: 000000000001869f x14: 0000000000000007 x15: 00000000ffffffff x16: 000000007ff439a5 x17: 000000007ff5730c x18: 000000007bea9de0 x19: 000000007ff7a580 x20: 000000007bec79f8 x21: 0000000000000000 x22: 000000007bea3580 x23: 0000000000000000 x24: 0000000000000000 x25: 000000007bec7a00 x26: 00000000ffffffc0 x27: 000000007bec79d0 x28: 000000007beb51c0 x29: 000000007bea3480 Code: 91246800 940130c2 12800000 1400004f (b9402ae0) Resetting CPU ... Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: net: octeontx: fix QSGMIITim Harvey2021-04-201-13/+7
| | | | | | | Revert a change that occured between the Marvell SDK-10.1.1.0 and SDK-10.3.1.1 which broke QSMII phy support. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* Fix IDE commands issued, fix endian issues, fix non MMIOReinoud Zandijk2021-04-201-109/+43
| | | | | | | | | | | | | | | | | | | | Fixes IDE issues found on the Malta board under Qemu: 1) DMA implied commands were sent to the controller in stead of the PIO variants. The rest of the code is DMA free and written for PIO operation. 2) direct pointer access was used to read and write the registers instead of the inb/inw/outb/outw functions/macros. Registers don't have to be memory mapped and ATA_CURR_BASE() does not have to return an offset from address zero. 3) Endian isues in ide_ident() and reading/writing data in general. Names were corrupted and sizes misreported. Tested malta_defconfig and maltael_defconfig to work again in Qemu. Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* misc: make CONFIG_IRQ selectable for all platformsWasim Khan2021-04-201-3/+2
| | | | | | | | | UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* phy: meson-g12a-usb3-pcie: add support for PCIe opsNeil Armstrong2021-04-201-4/+77
| | | | | | Add the PCIe part of the G12A USB3 PCIe Combo PHY driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson-g12a: add PCIe gatesNeil Armstrong2021-04-201-0/+2
| | | | | | Add missing gates used for PCIe. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banksEugen Hristev2021-04-191-0/+22
| | | | | | | | Add support for sama7g5 pinctrl variant, with 5 banks with a degraded 8 line only 5th bank. Based on Linux Kernel implementation. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini2021-04-184-176/+285
|\ | | | | | | | | | | | | | | This is a patchset which makes away with the .bind() controller indexing workaround which was broken since before v2021.04, and then adds PHY support and MX8M support on top of that. Better add it into the release early to get as much testing as possible done, because this really does a lot of changes to the ehci-mx6 driver.
| * usb: ehci-mx6: Add iMX8M supportMarek Vasut2021-04-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The iMX8M uses nop PHY, select PHY and NOP_PHY automatically. Otherwise, the DM capable driver is now perfectly compatible. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Fix aarch64 build warningsMarek Vasut2021-04-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix cast from pointer to integer of different size by casting the pointer to uintptr_t instead of uint32_t, the former has correct size on both 32bit and 64bit architectures. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Add fsl,imx7d-usb compatible stringMarek Vasut2021-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add new compatible string, used by some more up-to-date DTs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Set default CONFIG_MXC_USB_PORTSC if not definedMarek Vasut2021-04-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in config, to reduce the duplication. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Add generic EHCI PHY supportMarek Vasut2021-04-181-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | In case PHY support is enabled, use the generic EHCI PHY support to start and stop the PHY. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Use portnr from DT in DM caseMarek Vasut2021-04-181-45/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the platform uses DM, determine port number, which is used as offset in USBMISC registers, from PHY node DT aliases, just like Linux does. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Pass MISC address to usb_oc_config()Marek Vasut2021-04-181-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing ad-hoc sequence number to usb_oc_config(), pass in the USB MISC address itself. The USB MISC address comes from DT in DM case, and from the old method using controller index in non-DM case. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Split usb_power_config()Marek Vasut2021-04-181-51/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP addresses instead of ad-hoc sequence numbers. This is only applicable on legacy systems which do not implement proper PHY support. Once PHY support is available, parts of this can be removed altogether and moved to the PHY driver, similar to Linux phy-mxs-usb.c . Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Pass PHY address to usb_*_phy*()Marek Vasut2021-04-181-19/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing ad-hoc index to USB PHY handling functions and then try and figure out the PHY address, pass in the PHY address itself. For DM case, this address comes easily from DT. For non-DM case, the previous method is still present, however the non-DM case will soon be removed. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Split ehci_mx6_common_init()Marek Vasut2021-04-181-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pass component addresses around easily instead of passing ad-hoc sequence numbers, it is necessary to split ehci_mx6_common_init(). Make it so and call the separate functions instead. Since board_ehci_hcd_init() makes no sense in DM case, do not call it in DM case. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Parse USB PHY and MISC offsets from DTMarek Vasut2021-04-181-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case DM and OF controler is enabled, but PHY support is disabled, parse USB PHY and MISC component addresses from DT manually. Those component addresses will be used in subsequent patches to access the ANATOP, PHY and MISC registers matching the controller and thus get rid of the ad-hoc controller sequence number mapping. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Unify USBNC registersMarek Vasut2021-04-181-34/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Merge USBNC register layout structure into a single one, instead of having three separate structures and a lot of ifdeffery. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Add DM clock supportMarek Vasut2021-04-181-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add support for using DM clock framework to enable and disable all the necessary clock for the USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * usb: ehci-mx6: Turn off Vbus on probe failureMarek Vasut2021-04-181-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | The driver turns on Vbus regulator in probe, but fails to turn it back off in case of probe failure. Add the missing code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * imx: power-domain: Add fsl,imx8mn-gpc compatible stringMarek Vasut2021-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | The driver is compatible with iMX8MN, add missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * imx: power-domain: Add fsl,imx8mm-gpc compatible stringMarek Vasut2021-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | The driver is compatible with iMX8MM, add missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| * phy: nop-phy: Add standard usb-nop-xceiv compat stringMarek Vasut2021-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is compatible with USB no-op PHY, so add the compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
* | Merge tag 'ti-v2021.07-rc1' of ↵Tom Rini2021-04-181-60/+414
|\ \ | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Support for pinmux status command on beaglebone - Updates for MMC speed modes for J721e-evm - Fix MMC booting on omap35_logic_somlv board
| * | test: pinmux: add test for 'pinctrl-single' driverDario Binacchi2021-04-121-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test adds two pinmux nodes to the device tree, one to test when a register changes only one pin's mux (pinctrl-single,pins), and the other to test when more than one pin's mux is changed (pinctrl-single,bits). This required replacing the controller's register access functions when the driver is used on sandbox. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: add get_pin_muxing operationDario Binacchi2021-04-121-9/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: add get_pin_name operationDario Binacchi2021-04-121-0/+16
| | | | | | | | | | | | | | | | | | | | | It returns the name of the requested pin. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: add get_pins_count operationDario Binacchi2021-04-121-0/+37
| | | | | | | | | | | | | | | | | | | | | It returns the number of selectable pins. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: add register access functionsDario Binacchi2021-04-121-25/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | The configuration of pinmux registers was implemented with duplicate code which can be removed by adding two functions for read/write access. Access to 8-bit registers has also been added. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: change function mask default valueDario Binacchi2021-04-121-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch is inspired by more recent versions of the Linux driver. Replacing the default value 0xffffffff of the function mask with 0 is certainly more conservative in case the "pinctrl-single,function-mask" DT property is missing. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: check "register-width" DT propertyDario Binacchi2021-04-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In more recent versions of the Linux kernel the driver's probe function returns an error if the "pinctrl-single,register-width" DT property is missing. The lack of this information, in fact, does not allow to know whether to access the registers of the controller at 8, 16, ... bits. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: single: get register area size by device APIDario Binacchi2021-04-121-6/+8
| | | | | | | | | | | | | | | | | | | | | Use dev_read_addr_size to get size of the controller's register area. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
| * | pinctrl: single: fix debug messages formattingDario Binacchi2021-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", &reg, val); prints the 'reg' address preceded by the prefix 0x0x instead of 0x. This because the printf '%pa' format specifier already prepends the prefix '0x' to the address displayed. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
| * | pinctrl: single: fix offset managementDario Binacchi2021-04-121-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux configuration DT node of a peripheral does not define a physical address but an offset. Only by adding it to the base address of the controller it is possible to calculate the physical address of the register to be configured. Printing an offset also requires a different formatting option than a physical address. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
| * | pinctrl: single: fix the loop counter variable typeDario Binacchi2021-04-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'n' variable is used as a loop counter, not as a physical address, and is used in a comparison with an int. So it makes sense to change its type from phys_addr_t to int. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
generated by cgit (git 2.34.1) at 2025-09-01 09:16:35 +0000