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| * ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issuesDave Gerlach2021-05-121-717/+717
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issuesDave Gerlach2021-05-121-167/+167
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * mailbox: k3-sec-proxy: Extend valid thread IDsDave Gerlach2021-05-121-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | AM64x uses a different thread mapping that existing K3 SoCs, so update the valid thread ID list to include those used for AM64x. Also remove the comment identifying the purpose of each thread ID. The purpose of the thread ID is specified when describing the threads in the device tree and the same ID can mean different things on different SoCs, so the comment is not useful. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * mmc: sdhci_am654: Add Support for TI's AM642 SoCDave Gerlach2021-05-121-0/+18
| | | | | | | | | | | | | | | | | | | | Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi2021-05-125-24/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * clk: ti: am3-dpll: use custom API for memory accessDario Binacchi2021-05-121-33/+53
| | | | | | | | | | | | | | | | | | | | Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: gate: use custom API for memory accessDario Binacchi2021-05-121-11/+12
| | | | | | | | | | | | | | Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: change clk_ti_latch() signatureDario Binacchi2021-05-124-24/+28
| | | | | | | | | | | | | | | | | | The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add custom API for memory accessDario Binacchi2021-05-122-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | Merge tag 'u-boot-imx-20210502' of ↵Tom Rini2021-05-113-9/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210502 ------------------- - mx6: fixes for Ventana - local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec
| * | pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey2021-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | net: fec: Only unregister MII bus if we registered itSean Anderson2021-05-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we fail to probe for whatever reason, we cannot unregister/free the MII bus unless we registered it with fec_get_miibus. This fixes FECs sharing an MDIO bus from destroying it, preventing the other FEC from using it. Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | net: fec: Don't use disabled physSean Anderson2021-05-021-6/+9
| | | | | | | | | | | | | | | | | | | | | If a phy is disabled, don't use it. This matches Linux's behavior. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey2021-05-021-0/+6
| | | | | | | | | | | | | | | | | | | | | Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | pci: Update the highest subordinate bus number for bridge setupMasami Hiramatsu2021-05-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
* | | DM: DM_MMC migration is now mandatory for non-SPLTom Rini2021-05-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | As it has been now two years past the migration deadline, it is required to have migrated. Remove the check from the Makefile and rework some of the Kconfig logic slightly to get the functional dependencies of DM_MMC / BLK right in both the SPL and non-SPL case. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | ata: Make LIBATA means AHCI is enabled mandatory.Tom Rini2021-05-111-2/+4
| |/ |/| | | | | | | | | | | | | The migration deadline for having LIBATA mean that AHCI is also enabled was v2019.07. As that has long since passed, adjust the Kconfig dependencies. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-05-071-2/+8
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| * | atcspi200: Add timeout mechanism in spi_xfer()Dylan Jhong2021-05-051-2/+8
| |/ | | | | | | | | | | | | | | | | Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong <dylan@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | sysinfo: Add gpio-sysinfo driverSean Anderson2021-05-043-0/+150
| | | | | | | | | | | | | | | | This uses the newly-added dm_gpio_get_values_as_int_base3 function to implement a sysinfo device. The revision map is stored in the device tree. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sysinfo: Require that sysinfo_detect be called before other methodsSean Anderson2021-05-041-1/+28
| | | | | | | | | | | | | | | | | | | | This has the uclass enforce calling detect() before other methods. This allows drivers to cache information in detect() and perform (cheaper) retrieval in the other accessors. This also modifies the only instance where this sequencing was not followed. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sysinfo: Use global sysinfo IDs for existing sysinfo driversSean Anderson2021-05-042-4/+6
| | | | | | | | | | | | | | | | | | Since 07c9e683a4 ("smbios: Allow a few values to come from sysinfo") there are common global sysinfo IDs. This patch moved existing IDs above SYSINFO_ID_USER. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: gpio: Fix gpio_get_list_count failing with livetreeSean Anderson2021-05-041-3/+3
|/ | | | | | | | | | | | of_parse_phandle_with_args (called by dev_read_phandle_with_args) does not support getting the length of a phandle list by using the index -1. Instead, use dev_count_phandle_with_args which supports exactly this use-case. Fixes: 8558217153 ("gpio: Convert to use APIs which support live DT") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'dm-pull-29apr21' of ↵Tom Rini2021-04-297-24/+17
|\ | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-dm buildman environment fix binman FMAP improvements minor test improvements and fixes minor dm improvements
| * dm: core: Add size operations on device tree referencesChen Guanqiao2021-04-291-0/+11
| | | | | | | | | | | | | | | | | | | | Add functions to add size of addresses in the device tree using ofnode references. If the size is not set, return FDT_SIZE_T_NONE. Signed-off-by: Chen Guanqiao <chenguanqiao@kuaishou.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: core: Fix uninitialized return value from dm_scan_fdt_nodeSean Anderson2021-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | If there are no nodes or if all nodes are disabled, this function would return err without setting it first. Fix this by initializing err to zero. Fixes: 94f7afdf7e ("dm: core: Ignore disabled devices when binding") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: core: Add address translation in fdt_get_resourcePatrick Delaunay2021-04-295-23/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today of_address_to_resource() is called only in ofnode_read_resource() for livetree support and fdt_get_resource() is called when livetree is not supported. The fdt_get_resource() doesn't do the address translation so when it is required, but the address translation is done by ofnode_read_resource() caller, for example in drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() { ... ret = ofnode_read_resource(args.node, 0, &resource); if (ret) return ret; faddr = cpu_to_fdt32(resource.start); paddr = ofnode_translate_address(args.node, &faddr); ... The both behavior should be aligned and the address translation must be called in fdt_get_resource() and removed for each caller. Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device resources") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge tag 'xilinx-for-v2021.07-rc2' of ↵Tom Rini2021-04-293-6/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget)
| * | spi: zynqmp: Remove gd referenceMichal Simek2021-04-291-3/+0
| | | | | | | | | | | | | | | | | | gd is not used in this file that's why doesn't make sense to declare it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: phy: xilinx: Break while loop over ethernet phyMichal Simek2021-04-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") change driver behavior to while loop which wasn't correct because the driver was looping over again and again. The reason was that ofnode_valid() is taking 0 as correct value. Fix it by changing while loop to ofnode_for_each_subnode() which is only loop over available nodes. Fixes: 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | clk: Fix typo in Zynq Kconfig symbol descriptionMichal Simek2021-04-231-1/+1
| | | | | | | | | | | | | | | | | | Trivial typo fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini2021-04-291-5/+5
|\ \ \ | | | | | | | | | | | | - mtd: cfi: Fix PPB lock status readout (Marek)
| * | | mtd: cfi: Fix PPB lock status readoutMarek Vasut2021-04-281-5/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], the procedure to read out PPB lock bits is to send the PPB Entry, PPB Read, Reset/ASO Exit. Currently, the code does send incorrect PPB Entry, PPB Read and Reset/ASO Exit is completely missing. The PPB Entry sent is implemented by sending flash_unlock_seq() and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID. However, both [1] and [2] specify the last byte of PPB Entry as 0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID, that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY. Since this does make sense, this patch fixes it and thus also aligns the code in flash_get_size() with flash_real_protect(). The PPB Read returns 00h in case of Protected state and 01h in case of Unprotected state, according to [1] Note 83 and [2] Note 17, so invert the result. Moreover, align the arguments with similar code in flash_real_protect(). Finally, Reset/ASO Exit command should be executed to exit the PPB mode, so add the missing reset. [1] https://www.cypress.com/file/213346/download Document Number: 001-99198 Rev. *M Table 40. Command Definitions, Nonvolatile Sector Protection Command Set Definitions [2] https://www.cypress.com/file/177976/download Document Number: 001-98285 Rev. *R Table 7.1 Command Definitions, Nonvolatile Sector Protection Command Set Definitions Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips") Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* | | Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-04-2910-1280/+335
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done by Kostya) - Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell authors) - pci-aardvark: Fix processing PIO transfers (Pali)
| * | | arm: a37xx: pci: Fix processing PIO transfersPali Rohár2021-04-291-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen.fr/ https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | phy: marvell: utmi: update utmi config which fixes usb2.0 instabilityGrzegorz Jaszczyk2021-04-292-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: add support for SFI1Igal Liberman2021-04-292-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk2021-04-292-13/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: allow to initialize up to 6 USB portsGrzegorz Jaszczyk2021-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
| * | | phy: marvell: cp110: mark u-boot power-off callsIgal Liberman2021-04-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: fix handling of unconnected comphyChristine Gharzuzi2021-04-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: pass sgmii id to firmwareIgal Liberman2021-04-291-22/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware. Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: cp110: clean up driver after it was moved to atfGrzegorz Jaszczyk2021-04-295-777/+0
| | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
| * | | phy: marvell: cp110: remove both phy and pipe selector configurationGrzegorz Jaszczyk2021-04-291-94/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode. Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
| * | | phy: marvell: cp110: let the firmware perform training for XFIGrzegorz Jaszczyk2021-04-291-179/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Igal Liberman <igall@marvell.com>
| * | | phy: marvell: cp110: let the firmware configure comphy for USBGrzegorz Jaszczyk2021-04-291-124/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| * | | phy: marvell: cp110: let the firmware configure comphy for RXAUIGrzegorz Jaszczyk2021-04-291-180/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the comphy initialization for RXAUI with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
| * | | phy: marvell: cp110: remove unused definitionsMarcin Wojtas2021-04-292-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | phy: marvell: enable comphy info prints for all devicesIgal Liberman2021-04-291-2/+1
| | | | | | | | | | | | | | | | | | | | Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743 Signed-off-by: Igal Liberman <igall@marvell.com>
| * | | phy: marvell: add RX training commandIgal Liberman2021-04-294-3/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
generated by cgit (git 2.34.1) at 2025-08-30 21:49:11 +0000