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* Revert "spi: atmel: Drop non-dm code"Tom Rini2018-04-072-0/+217
| | | | | | | | | As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 7b0947787358c6b277431d6b76ce043d8bec641d. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "spi: atmel: Drop atmel_spi.h"Tom Rini2018-04-072-88/+93
| | | | | | | | | As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 37434db29be495ef41f204a97b8bf13b1418f97d. Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: uclass: Fix debug stringMario Six2018-04-061-1/+1
| | | | | | | | A debug string still has the old name of a function being called; update it. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* watchdog: Fix Kconfig alignment for WDT_SANDBOXMichal Simek2018-04-061-3/+3
| | | | | | | Fix Kconfig alignment which should be <tab><space><space>. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rtc: rx8025: remove redundant code in rtc_resetChris Packham2018-04-061-17/+1
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the rx8025 implementation of rtc_reset() does not need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com>
* rtc: rs5c372: remove redundant code in rtc_resetChris Packham2018-04-061-23/+1
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the rs5c372 implementation of rtc_reset() does not need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com>
* rtc: mx27rtc: remove redundant code in rtc_resetChris Packham2018-04-061-5/+1
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the mx27rtc implementation of rtc_reset() can be an empty stub function. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* rtc: ds1374: remove redundant code in rtc_resetChris Packham2018-04-061-15/+0
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the ds1374 implementation of rtc_reset() doesn't need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com>
* rtc: ds1307: remove redundant code in rtc_resetChris Packham2018-04-061-33/+0
| | | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the ds1307 implementation of rtc_reset() doesn't need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clock: stm32mp1: add stgen clock source change supportPatrick Delaunay2018-04-061-1/+45
| | | | | | | | The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* rtc: rewrite isl1208 to support DMKlaus Goger2018-04-062-55/+98
| | | | | | | | | | Adds devicemodel support to the ISL1208 driver. This patch drops the non-dm API as no board was using it anyway. Also add it to Kconfig. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* regulator: pbias: don't evaluate variable before assignmentHeinrich Schuchardt2018-04-061-3/+3
| | | | | | | We should not evaluate the value of reg before its value is set. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* input: Drop PS/2 keyboard supportSimon Glass2018-04-065-950/+0
| | | | | | | This is not used by any current board and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers: serial: remove nonexisting initialisation functionsChristophe Leroy2018-04-061-64/+0
| | | | | | | This patch removes call of serial initialisation functions that are not implemented anymore. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* Migrate CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSCAlex Kiernan2018-04-061-0/+1
| | | | | | This converts CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC to Kconfig Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
* powerpc: mpc8xx: move watchdog into drivers/watchdogChristophe Leroy2018-04-062-0/+22
| | | | | | In preparation of DM watchdog, move basic actions into drivers/watchdog Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* powercp: mpc8xx: move commproc.hChristophe Leroy2018-04-063-3/+3
| | | | | | | include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and move it into arch/powerpc/include/asm Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xxChristophe Leroy2018-04-063-3/+3
| | | | | | | | | CONFIG_8xx doesn't mean much outside of arch/powerpc/ This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ... It also renames 8xx_immap.h to immap_8xx.h to be consistent with other file names. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* soft_i2c: cleanup - no mpc8xx supportChristophe Leroy2018-04-061-3/+0
| | | | | | | commit 907208c452999 ("powerpc: Partialy restore core of mpc8xx") didn't bring back support for I2C on the mpc8xx Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* spi: atmel: default y if DM_SPI && ARCH_AT91Jagan Teki2018-04-061-1/+1
| | | | | | | | | ATMEL_SPI is now fully converted to driver-model and respective boards switch to DM_SPI as well, so make default y for ARCH_AT91 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
* spi: atmel: Drop atmel_spi.hJagan Teki2018-04-062-93/+88
| | | | | | | | | atmel_spi.h has register offsets, and atmel_spi_slave structure, move it into .c file for better readability and drop atmel_spi.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
* spi: atmel: Drop non-dm codeJagan Teki2018-04-062-217/+0
| | | | | | | | All board configs are now enabled DM_SPI for SPL and U-Boot proper, so now its time to drop non-dm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
* spi: atmel: Add ifdef for DM_GPIO codeJagan Teki2018-04-061-2/+12
| | | | | | | | | Few boards are configuring gpio directly from board instead using drivers/gpio so add ifdef for DM_GPIO to compatible for both the cases. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
* Merge tag 'signed-rpi-next' of git://github.com/agraf/u-bootTom Rini2018-04-062-2/+3
|\ | | | | | | | | | | | | | | | | Patch queue for rpi - 2018-04-06 Highlights this time around: - Support for new RPi3 B+ model - Fix for some SD cards on newer RPi firmware
| * mmc: use core clock frequency in bcm2835 sdhostJonathan Gray2018-04-052-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and later start.elf now sets the EMMC clock to 200 MHz. According to Phil Elwell in https://github.com/raspberrypi/firmware/issues/953 the SDHost controller shares the core/VPU clock and doesn't use the EMMC clock. Use the core clock id when determining the frequency to allow U-Boot to work with recent versions of raspberrypi-firmware. Otherwise U-Boot hangs at: U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100) DRAM: 948 MiB RPI 3 Model B (0xa02082) MMC: mmc@7e202000: 0, sdhci@7e300000: 1 Loading Environment from FAT... Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2018-04-046-146/+218
|\ \ | |/ |/| | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * sunxi: revert disabling of featuresAndre Przywara2018-04-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | In January some commits were introduced to mitigate the U-Boot image size issues we encountered on sunxi builds. Now with the MMC environment removed we can bring them back, as we practically don't have a size limit anymore. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * net: sun8i-emac: remove support for old bindingAndre Przywara2018-04-041-53/+25
| | | | | | | | | | | | | | | | | | | | | | The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * net: sun8i-emac: add support for new EMAC DT bindingAndre Przywara2018-04-041-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * net: sun8i-emac: support new pinctrl DT bindingsAndre Przywara2018-04-041-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: gpio: add missing compatible stringsAndre Przywara2018-04-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi GPIO driver is missing some compatible strings for recent SoCs. While most of the sunxi GPIO code seems to not rely on this (and so works anyway), the sunxi_name_to_gpio() function does and fails at the moment (for instance when resolving the MMC CD pin name). Add the compatible strings for the A64 and V3s, which were missing from the list. This now covers all pinctrl nodes in our own DTs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: move the NAND parameters to KconfigMiquel Raynal2018-04-031-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the NAND parameters from defconfig files to Kconfig for SUNXI architecture only. Fort now only the CHIP pro is migrated. It would have been better to convert this defconfig entry to Kconfig for all supported machines/architectures but it has been abandoned due to a fairly high amount of errors reported by the moveconfig.py tool. This is due to defines quite often being multiplications of values/other defines not correctly handled. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * sunxi: make NAND_SUNXI use ARCH_SUNXI as default in KconfigMiquel Raynal2018-04-031-0/+1
| | | | | | | | | | | | | | | | | | Remove NAND_SUNXI from the CHIP pro defconfig to be automatically selected depending on the state of ARCH_SUNXI. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * sunxi: automatically select SPL_NAND_SUPPORT in KconfigMiquel Raynal2018-04-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the number of entries to add in defconfig files when adding NAND support. For now, the only board using it is the CHIP pro. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * sunxi: allow NAND support to be compiled for sun8i platformsMiquel Raynal2018-04-031-1/+1
| | | | | | | | | | | | | | | | Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I in Kconfig. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: use PIO instead of DMAMiquel Raynal2018-04-031-80/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL support was first written to support only the earlier generations of Allwinner SoCs, and was only really enabled on the A13 / GR8. However, those old SoCs had a DMA engine that has been replaced since the A31 by another DMA controller that is no longer compatible. Since the code directly uses that DMA controller, it cannot operate properly on the later SoCs, while the NAND controller has not changed. There's two paths forward, the first one would have been to add support for that DMA controller too, the second to just remove the DMA usage entirely and rely on PIO. The later has been chosen because CPU overload at this stage is not an issue and it makes the driver more generic, and easier to understand. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: declare the ecc_bytes array globallyMiquel Raynal2018-04-031-1/+2
| | | | | | | | | | | | | | | | | | Move the ecc_bytes array out of nand_max_ecc_strength() for future use by nand_read_page(). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: make the reset column helper more genericMiquel Raynal2018-04-031-5/+5
| | | | | | | | | | | | | | | | | | | | | | Prepare the future use of an helper to move the data pointer (the column) of the NAND chip by renaming nand_reset_column() to nand_change_column(). Resetting the column is just a matter of giving 0 as argument. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: ensure enough time has passed after changing the columnMiquel Raynal2018-04-031-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | When changing the column, the ONFI specification states that a minimum time of tCCS (Change Column Setup time) must elapse between the last address cycle is asserted on the bus and the first data cycle is clocked. An usual value for average NANDs is 500 nanoseconds. Round it up to 1 microsecond to be safe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: create an helper to handle command executionMiquel Raynal2018-04-031-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Executing a command is matter of always doing the following sequence: * Waiting for the FIFO to be empty so we can fill it with the new command. * Clearing the status register. * Writing the command in the FIFO. * Waiting for the command to finish. Add a nand_exec_cmd() helper to handle this instead of repeating the logic through the various functions. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: add missing status clearMiquel Raynal2018-04-031-0/+1
| | | | | | | | | | | | | | | | | | It is best practice to always clear the status register before executing a command to be sure that the status read afterwards is relevant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helperMiquel Raynal2018-04-031-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | One bit in the control registers indicates if the NAND controller is ready to receive a new command. Otherwise, the command FIFO is full and we should wait for this bit to flip. It then states that the last command has been processed and the FIFO is now free to welcome another command. Add this sanity check before starting any new command. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: introduce the nand_wait_int() helperMiquel Raynal2018-04-031-20/+14
| | | | | | | | | | | | | | | | | | | | | | The pattern of polling on a status register until a bit is set or a timeout occurs is repeated multiple times in the driver. Mutualize the code by introducing the nand_wait_int() helper that does wait for the bit to flip or returns an error in case of timeout. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: fix typo on register nameMiquel Raynal2018-04-031-3/+3
| | | | | | | | | | | | | | | | Change NFC_SEND_ADR to NFC_SEND_ADDR. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * spl: nand: sunxi: fix second case of modulo by zero errorMiquel Raynal2018-04-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the nand_read_buffer() step, the seed is calculated by doing a modulo by conf->nseeds which is always zero when not using the randomizer (most of SLC NANDs). This situation turns out to lead to a run time freeze with certain toolchains. Derive this seed only when the randomizer is enabled (and conf->nseeds logically not zero), exactly like what has been done before with an identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo by zero error"). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * mtd: nand: sunxi: fix ECC strength choiceMiquel Raynal2018-04-031-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the requested ECC strength does not exactly match the strengths supported by the ECC engine, the driver is selecting the closest strength meeting the 'selected_strength > requested_strength' constraint. Fix the fact that, in this particular case, ecc->strength value was not updated to match the 'selected_strength'. For instance, one can encounter this issue when no ECC requirement is filled in the device tree while the NAND chip minimum requirement is not a strength/step_size combo natively supported by the ECC engine. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2018-04-015-26/+57
|\ \
| * | core: ofnode: Fix translation for #size-cells == 0Mario Six2018-04-012-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 286ede6 ("drivers: core: Add translation in live tree case") made dev_get_addr always use proper bus translations for addresses read from the device tree. But this leads to problems with certain busses, e.g. I2C busses, which run into an error during translation, and hence stop working. It turns out that of_translate_address() and fdt_translate_address() stop the address translation with an error when they're asked to translate addresses for busses where #size-cells == 0 (comment from drivers/core/of_addr.c): * Note: We consider that crossing any level with #size-cells == 0 to mean * that translation is impossible (that is we are not dealing with a value * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things To fix this case, we check in both the live-tree and non-live tree-case, whether the bus of the device whose address is about to be translated has size-cell size zero. If this is the case, we just read the address as a plain integer and return it, and only apply bus translations if the size-cell size if greater than zero. Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Reported-by: Martin Fuzzey <mfuzzey@parkeon.com> Fixes: 286ede6 ("drivers: core: Add translation in live tree case") Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: core: make fixed-clock dt scan live dt compatibleAndy Yan2018-04-011-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | dm_scan_fdt_node can't work when live dt is active, we should use dm_scan_fdt_live instead. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pinctrl-uclass: convert to use live dtKever Yang2018-03-311-14/+5
| | | | | | | | | | | | | | | | | | | | | Use live dt interface for pinctrl_select_state_full() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit (git 2.34.1) at 2024-12-29 08:21:14 +0000