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* | | | Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dmTom Rini2019-11-013-6/+9
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | - Fix for patman with email addresses containing commas - Bootstage improvements for TPL, SPL - Various sandbox and dm improvements and fixes
| * | | fdt: Fix alignment issue when reading 64-bits properties from fdtJean-Jacques Hiblot2019-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FDT specification [0] gives a requirement of aligning properties on 32-bits. Make sure that the compiler is aware of this constraint when accessing 64-bits properties. [0]: https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Update log method for uclass_find_device_by_seqKever Yang2019-10-271-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use log() insted of debug() for uclass_find_device_by_seq function, since this print is very much and we can filter it out with log() interface. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Move #define to top of file as per docs: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: regmap: Fix mask in regmap_update_bits()Simon Glass2019-10-271-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | This function assumes that the 'val' parameter has no masked bits set. This is not defined by the function prototype though. Fix the function to mask the value and update the documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* | | drivers: phy: Handle gracefully NULL pointersJean-Jacques Hiblot2019-10-311-5/+25
| | | | | | | | | | | | | | | | | | | | | For some controllers PHYs can be optional. Handling NULL pointers without crashing nor failing, makes it easy to handle optional PHYs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* | | ata: ahci allow 64-bit DMA for SATARoman Kapl2019-10-311-3/+11
| | | | | | | | | | | | | | | | | | | | | Allow 64-bit DMA on AHCI. If not supported by the host controller, at least print a message and fail. Signed-off-by: Roman Kapl <rka@sysgo.com>
* | | nvme: use page-aligned buffer for identify commandPatrick Wildt2019-10-311-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the stack-allocated buffer for the identification command to explicitly allocate page-aligned buffers. Even though the spec seems to allow having admin queue commands on non page-aligned buffers, it seems to not be possible on my i.MX8MQ board with a a Silicon Power P34A80. Since all of the NVMe drivers I have seen always do admin commands on a page-aligned buffer, which does work on my system, it makes sense for us to do that as well. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: flush dcache on both r/w, and the prp listPatrick Wildt2019-10-311-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's possible that the data cache for the buffer still holds data to be flushed to memory, since the buffer was probably used as stack before. Thus we need to make sure to flush it also on reads, since it's possible that the cache is automatically flused to memory after the NVMe DMA transfer happened, thus overwriting the NVMe transfer's data. Also add a missing dcache flush for the prp list. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | virtio: pci: use correct type in virtio_pci_bind()Heinrich Schuchardt2019-10-311-1/+1
| | | | | | | | | | | | | | | | | | | | | For printing as %u we should use an unsigned int. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | gpio: da8xx_gpio: Fix the _gpio_direction_output functionKeerthy2019-10-301-7/+7
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | _gpio_direction_output function currently calls gpio_set_value with the wrong gpio number. gpio_set_value in the uclass driver expects a different gpio number and the _gpio_direction_output is currently providing the number specific to the bank. Hence fix it by calling the _gpio_set_value function instead. Reported-by: Faiz Abbas <faiz_abbas@ti.com> Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci") Signed-off-by: Keerthy <j-keerthy@ti.com>
* | Merge tag 'u-boot-clk-23Oct2019' of ↵Tom Rini2019-10-308-58/+280
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add I2C clocks for i.MX6Q CCF driver - Fix check in clk_set_default_parents() - Managed API to get clock from device tree - Fixes for core clock code (including sandbox regression tests)
| * | test: clk: test clock self assignmentJean-Jacques Hiblot2019-10-221-0/+22
| | | | | | | | | | | | | | | | | | | | | Make sure that the clock self-assignment works by having a clock of clk-sbox be configured automatically when clk-sbox is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | drivers: clk: Fix using assigned-clocks in the node of the clock it sets upJean-Jacques Hiblot2019-10-222-7/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | test: clk: Update tests to also check the managed APIJean-Jacques Hiblot2019-10-222-9/+91
| | | | | | | | | | | | | | | | | | | | | | | | Add a few more clocks the clk_sandbox clock provider and get them using the managed API. Make sure they are released when the device is removed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | drivers: clk: Add a managed API to get clocks from the device-treeJean-Jacques Hiblot2019-10-223-34/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add devm_clk_get(), devm_clk_get_optional() to get clocks from the device-tree. The clocks is automatically released and the data structure freed when the device is unbound. Also add devm_clk_put() to release the clock and free the data structure manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | drivers: clk: Handle gracefully NULL pointersJean-Jacques Hiblot2019-10-221-7/+36
| | | | | | | | | | | | | | | | | | | | | Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | clk: Add support for I2C clocks on NXP's imx6q SoC which use CCFLukasz Majewski2019-10-222-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for I2C clock modeled in CCF. This code intention is to only enable those clocks in the I2C driver with default settings. For that reason the "busy" versions of clocks reuse the generic approach and would need to be updated when one wants to adjust the I2C clock frequency in U-Boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * | clk: Fix error check in clk_set_default_parents()Jean-Jacques Hiblot2019-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | According to the documentation in clk.h, clk_set_parent() return the new rate of the clock or a negative error code. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* | | Merge tag 'mmc-10-29-2019' of ↵Tom Rini2019-10-301-40/+3
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc driver cleanup - spl_mmc bug fix to avoid access wrong emmc partition
| * | | mmc: fsl_esdhc: drop i.MX DDR support codeYangbo Lu2019-10-291-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode, and hasn't been supported. Let's drop DDR support code for i.MX in fsl_esdhc driver. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | | mmc: fsl_esdhc: remove redundant DM_MMC checkingYangbo Lu2019-10-291-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | | mmc: fsl_esdhc: make BLK as hard requirement of DM_MMCYangbo Lu2019-10-291-32/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2019-10-3014-28/+74
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | - H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
| * | spi-nor-ids: Add support for Adesto AT25SL321Fabio Estevam2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTDFrieder Schrempf2019-10-253-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in SPL. They often rely on hacks in the board header files to include this option conditionally. To be able to fix this, we previously introduced a separate option SPL_SPI_FLASH_MTD. Therefore we can now adjust the Makefile and change the code in sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD). We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the header files to the according defconfigs. The affected boards are socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6 and da850evm. We do this all in one patch to guarantee bisectibility. This change was tested with buildman to make sure it does not introduce any regressions by comparing the resulting binary sizes. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entryVignesh Raghavendra2019-10-251-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi-nor: spi-nor-ids: Add entries for mt25q variantsVignesh Raghavendra2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*Vignesh Raghavendra2019-10-251-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: designware_spi: Disable and free clock when remove driverLey Foon Tan2019-10-251-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with ↵Vignesh Raghavendra2019-10-252-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-core: Use dev_err for reporting erase/write failuresVignesh Raghavendra2019-10-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use dev_err() when reporting reason for erase/write failures so that users can be made aware of the reason for failure. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi: Add a new option SPL_SPI_FLASH_MTD to KconfigFrieder Schrempf2019-10-251-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | To allow SPI_FLASH_MTD being enabled separately in SPL we add a new option. The only user currently is the stm32mp15_basic board. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: Kconfig: Enable SPI_SUNXI for SUNXIJagan Teki2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASHJagan Teki2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DM_SPI_FLASH should require spi flash interface code for dm version, so imply SPI_FLASH core by default if any board enabled DM_SPI_FLASH. This overcome the explicit enablement of CONFIG_SPI_FLASH on respective boards when DM_SPI_FLASH being used. Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | dm: spi: Change cs_info op to return -EINVAL for invalid cs numBin Meng2019-10-255-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | dm: spi: Return 0 if driver does not implement ops->cs_infoBin Meng2019-10-251-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: Kconfig: Add help textJagan Teki2019-10-251-0/+17
| | | | | | | | | | | | | | | | | | Add detailed help text for SPI support. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor: ids: Add is25wp256 chipJagan Teki2019-10-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | mtd: spi: Kconfig: Update CONFIG_SPI_FLASHJagan Teki2019-10-251-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) CONFIG_SPI_FLASH is not just a legacy code, but it has common core code which handle both dm and non-dm spi flash code. So fix the info text to make it clear globally. 2) Since it's flash core it shouldn't depends on legacy SPI, so remove the 'depends on SPI' Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | | Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini2019-10-2526-436/+1812
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
| * | | mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao2019-10-251-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2019-10-252-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao2019-10-251-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2019-10-252-29/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao2019-10-251-37/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2019-10-252-68/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | reset: add reset controller driver for MediaTek MIPS platformWeijie Gao2019-10-253-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | pinctrl: add support for MediaTek MT7628Weijie Gao2019-10-257-0/+747
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | spi: mt7621-spi: restore default register value after each xferWeijie Gao2019-10-251-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
generated by cgit (git 2.34.1) at 2025-02-06 10:10:03 +0000