summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dmTom Rini2019-04-137-108/+92
|\ | | | | | | | | | | fdtdec tests and improvements for carve-outs pinctrl race-condition fix various other fixes in sandbox, sound, mkimage, etc.
| * dm: remove unused function dm_fdt_pre_relocPatrick Delaunay2019-04-111-23/+0
| | | | | | | | | | | | | | | | The function dm_ofnode_pre_reloc should be used instead of the function dm_fdt_pre_reloc and avoid duplicated code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+2
| | | | | | | | | | | | | | Prepare to remove dm_fdt_pre_reloc function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: at91: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+1
| | | | | | | | | | | | | | Prepare to remove dm_fdt_pre_reloc Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * core: ofnode: Fix ASAN-reported stack-buffer-overflow in of_get_addressEugeniu Rosca2019-04-111-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2019.04-rc3 sandbox U-Boot fails to boot when compiled with -fsanitize=address and linked against -lasan, reporting [1]. Git bisecting shows that the issue is contributed by v2019.01 commit 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function"). The root cause seems to be the mismatch between sizeof(u64) and sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the size argument of both of_get_address() and fdtdec_get_addr_size_fixed() is optional, we can pass NULL in its place, avoiding the problem. [1] Backtrace reported by ASAN (gcc 8.1.0): $> ./u-boot -d arch/sandbox/dts/sandbox.dtb [..] Reviewed-by: Simon Glass <sjg@chromium.org> ================================================================= ==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffcc2331140 at pc 0x0000004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70 WRITE of size 8 at 0x7ffcc2331140 thread T0 #0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154 #1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263 #2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422 #3 0x4dccd8 in device_probe drivers/core/device.c:407 #4 0x753170 in eth_initialize net/eth-uclass.c:428 #5 0x47d9bf in initr_net common/board_r.c:557 #6 0x6bcfa7 in initcall_run_list lib/initcall.c:30 #7 0x47e1fe in board_init_r common/board_r.c:859 #8 0x4060e5 in main arch/sandbox/cpu/start.c:356 #9 0x7fb8d135482f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f) #10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8) Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame #0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255 This frame has 3 object(s): [32, 36) 'size' <== Memory access at offset 32 partially overflows this variable [96, 100) 'flags' [160, 168) 'node' HINT: this may be a false positive if your program uses some custom stack unwind mechanism or swapcontext (longjmp and C++ exceptions *are* supported) SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154 in of_get_address Shadow bytes around the buggy address: 0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2 0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00 =>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2 0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3 0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3 0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb ==10998==ABORTING 'To' list: git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \ sed 's/.*-by: //' | sort | uniq -c | sort -rn 10 Simon Glass <sjg@chromium.org> 3 Mario Six <mario.six@gdsys.cc> 2 Martin Fuzzey <mfuzzey@parkeon.com> 2 Marek Vasut <marek.vasut+renesas@gmail.com> 1 Tom Rini <trini@konsulko.com> 1 Masahiro Yamada <yamada.masahiro@socionext.com> 1 Keerthy <j-keerthy@ti.com> 1 Jens Wiklander <jens.wiklander@linaro.org> 1 Bin Meng <bmeng.cn@gmail.com> Fixes: 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
| * sysreset: use syscon_regmap_lookup_by_phandlePatrick Delaunay2019-04-111-13/+2
| | | | | | | | | | | | | | Use the new function syscon_regmap_lookup_by_phandle() to simplify the code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * syscon: update syscon_regmap_lookup_by_phandlePatrick Delaunay2019-04-111-24/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the function syscon_regmap_lookup_by_phandle() introduced by commit 6c3af1f24e4b ("syscon: dm: Add a new method to get a regmap from DTS") to have Linux-compatible syscon API. Same modification than commit e151a1c288bd ("syscon: add Linux-compatible syscon API") solves issue when the node identified by the phandle has several compatibles and is already bound to a dedicated driver. See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon interface from platform devices"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind()Patrick Delaunay2019-04-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some binding define child node gpio-controller without compatible property. This patch avoid to bind the pinconfig uclass to these node. For example, the binding for st,stm32-pinctrl (./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl) but without compatible (as it is not mandatory). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: pinctrl: Avoid race condition on probe for UCLASS_PINCTRLPatrice Chotard2019-04-111-4/+7
| | | | | | | | | | | | | | | | | | | | | | In case of system with several pin-controller device, probe the first UCLASS_PINCTRL by seq number (defined by alias) to avoid race condition with I2C PINCONTROL driver for GPIO expander (GPIO expander need I2C bus, I2C driver need PINCONFIG). Signed-off-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().Christoph Muellner2019-04-111-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. As noted in the comment, the function pinctrl_decode_pin_config_dm() only served as a temporary solution. Since the function has no users anymore, we can remove it again. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: remove pre reloc properties in SPL and TPL device treePatrick Delaunay2019-04-112-24/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | We can remove the pre reloc property in SPL and TPL device-tree: - u-boot,dm-pre-reloc - u-boot,dm-spl - u-boot,dm-tpl As only the needed node are kept by fdtgrep (1st pass). The associated function (XXX_pre_reloc) are simple for SPL/TPL: return always true. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mipsTom Rini2019-04-1313-51/+2209
|\ \ | | | | | | | | | | | | | | | | | | | | | - mt76xx: add USB support, small fixes - ath79: small fixes, add support for QCA9563 SoC and AP152 reference board - mscc: small fixes, add network support for JR2 and ServalT SoCs - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs - MIPS: fix redundant relocation of initrd images
| * | phy: Add USB PHY driver for the MT76x8 (7628/7688) SoCStefan Roese2019-04-123-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | net: Add MSCC ServalT network driver.Horatiu Vultur2019-04-123-0/+630
| | | | | | | | | | | | | | | | | | | | | | | | Add network driver for Microsemi Ethernet switch. It is present on ServalT SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | net: Add MSCC Jaguar2 network driver.Horatiu Vultur2019-04-123-0/+1083
| | | | | | | | | | | | | | | | | | | | | | | | Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * | gpio: bcm6345: allow this driver on ARCH_BCM63158Philippe Reynes2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | This IP is also used on some arm SoC, so we allow to use this driver on arch bcm63158. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * | gpio: bcm6345: allow this driver on ARCH_BCM6858Philippe Reynes2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | This IP is also used on some arm SoC, so we allow to use this driver on arch bcm6858. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * | gpio: bcm6345: switch to raw I/O functionsPhilippe Reynes2019-04-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | ag7xxx: add initial support for s17Rosy Song2019-04-121-16/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | S17 ethernet support is for QCA8337N, which used on AP152 (QCA9563) board. It is a 7 ports GbE switch. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more commit message for s17 Changes for v4-v5: - coding style cleanup
| * | dma: bcm6348: check if driver is enabled before send/recvÁlvaro Fernández Rojas2019-04-121-0/+6
| | | | | | | | | | | | | | | | | | This patch prevents errors when running tftpput. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * | net: mscc: ocelot: Fix reset of the physHoratiu Vultur2019-04-121-17/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | drivers: add ethernet support for qca953x in ag7xxx driverRosy Song2019-04-121-17/+186
| | | | | | | | | | | | Signed-off-by: Rosy Song <rosysong@rosinson.com>
| * | drivers: fix typo for pinctrl qca953xRosy Song2019-04-121-1/+1
| |/ | | | | | | Signed-off-by: Rosy Song <rosysong@rosinson.com>
* | Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-bootTom Rini2019-04-1219-1159/+2774
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stm32 patches for v2019.07-rc1 - Add trusted boot with TF-A for stm32mp1 - stm32mp1 dts files sync'ed with Linux version - add STM32MP1 Discovery boards (DK1 and DK2) - add STMFX gpio expander driver - misc improvement for stm3mp1 supports - rename stpmu1 to stpmic1 (official name) - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu) - add STM32 FMC2 NAND flash controller driver
| * | mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driverChristophe Kerello2019-04-123-0/+1104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
| * | spi: stm32_qspi: move to exec_opChristophe Kerello2019-04-122-383/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are facing issues in the driver since SPI NOR framework has moved on SPI MEM framework, and SPI NAND framework is not running properly with the current driver. To be able to solve issues met on SPI NOR Flashes and to be able to support SPI NAND Flashes, the driver has been reworked. We are now using exec_op ops instead of using xfer ops. Thanks to this rework, the driver has been successfully tested with: - mx66l51235l SPI NOR Flash on stm32f746 SOC - n25q128a SPI NOR Flash on stm32f769 SOC - mx66l51235l SPI NOR Flash on stm32mp1 SOC - mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
| * | pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverPatrick Delaunay2019-04-123-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on UCLASS_PINCTRL and UCLASS_GPIO. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * | stpmic1: add NVM update support in fuse commandPatrick Delaunay2019-04-122-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to read/update the non volatile memory of STPMIC1 (8 bytes-register at 0xF8 address) and allow access with fuse command (bank=1, word > 0xF8). For example: STM32MP> fuse read 1 0xf8 8 Reading bank 1: Word 0x000000f8: 000000ee 00000092 000000c0 00000002 Word 0x000000fc: 000000f2 00000080 00000002 00000033 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | pmic: stpmu1: add power switch off supportPatrick Delaunay2019-04-121-0/+46
| | | | | | | | | | | | | | | | | | | | | Add sysreset support, and support power switch off request, needed by poweroff command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stpmic1: update register namesPatrick Delaunay2019-04-121-57/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | power: rename stpmu1 to official name stpmic1Patrick Delaunay2019-04-126-292/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | power: stpmu1: rename files to stpmic1Patrick Delaunay2019-04-124-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Prepare file modification for kernel alignment and rename driver to stpmic1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | regulator: stpmu1: update buck1 rangePatrick Delaunay2019-04-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | SW impact for Rev 1.2 of STPMIC1 in U-Boot: Buck converters output voltage change for Buck1 => Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V (see STPMIC1 datasheet / chapter 5.3 Buck converters) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: add trusted boot with TF-APatrick Delaunay2019-04-122-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2019-04-125-11/+79
|\ \ \
| * | | misc: i2c_eeprom: add eeprom write supportBaruch Siach2019-04-111-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Write up to page size in each i2c transfer. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | misc: i2c_eeprom: support DT pagesize propertyBaruch Siach2019-04-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the page size from DT when available. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | i2c: muxes: pca954x: support PCA9543 I2C switchLuca Ceresoli2019-04-112-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCA9543 is a 2-channel I2C switch. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher<hs@denx.de>
| * | | i2c: muxes: pca954x: clarify enable fieldLuca Ceresoli2019-04-111-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chip_desc.enable field is used only for muxes, not for switches. Document it and remove the unused values. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher<hs@denx.de>
| * | | i2c: muxes: pca954x: update list of supported devicesLuca Ceresoli2019-04-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig help has not been updated while adding PCA9547 and PCA9646. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher<hs@denx.de>
| * | | DM: I2C: Introduce 'u-boot, i2c-transaction-bytes' propertyLukasz Majewski2019-04-112-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'u-boot,i2c-transaction-bytes' device tree property provides information regarding number of bytes transferred by a device in a single transaction. This change is necessary to avoid hanging devices after soft reset. One notable example is communication with MC34708 device: 1. Reset when communicating with MC34708 via I2C. 2. The u-boot (after reboot -f) tries to setup the I2C and then calls force_idle_bus. In the same time MC34708 still has some data to be sent (as it transfers data in 24 bits chunks). 3. The force_idle_bus() is not able to make the bus idle as 8 SCL clocks may be not enough to have the full transmission. 4. We end up with I2C inconsistency with MC34708. This PMIC device requires 24+ SCL cycles to make finish any pending I2C transmission. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | | | Merge git://git.denx.de/u-boot-marvellTom Rini2019-04-126-161/+228
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Misc dts files sync'ed with Linux version (Chris) - Orion watchdog fix (Chris) - kwbimage changed to also support Marvell bin_hdr binary (Chris) - Add DM support to enable CONFIG_BLK for sata_mv (Stefan) - Enable BLK on multiple platforms (Stefan) - Misc minor fixes to AXP theadorable board (Stefan) - Correct logic for DM_SCSI + unconverted drivers check (stefan) - Misc changes to kirkwood to enable DM_USB here (Chris) - Change ahci_mvebu to enable usage on A38x (Baruch) - Update the kirkwood entry in git-mailrc (Baruch) - Misc minor improvements (turris, documentation) (Baruch) - Enhance sata_mv to support Kirkwood as well (Michael) - Add wdt command (Michael) - Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG board support (Chris)
| * | | | arm: mvebu: Add Marvell's integrated CPUsChris Packham2019-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | sata: sata_mv: add orion-sata compatible stringMichael Walle2019-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kirkwood devices are compatible with this driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | sata: sata_mv: support kirkwood architectureMichael Walle2019-04-121-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the worng include and offset macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | sata: sata_mv: use correct format specifier in debug()Michael Walle2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a compile error on kirkwood. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ata: ahci_mvebu: add support for Armada 38xBaruch Siach2019-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With board_ahci_enable() implementation for Armada 38x in place we can now enable 38x support in the ahci_mvebu driver. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | sata: sata_mv: Add DM support to enable CONFIG_BLK usageStefan Roese2019-04-122-149/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM support to the Armada XP SATA driver. This is needed to enable CONFIG_BLK on this platform. It adds the SATA controller as AHCI device, which is strictly speaking not correct, as the controller is not AHCI compatible. But the U-Boot AHCI uclass interface enables the usage of this DM driver and the creation of the corresponding BLK devices. This conversion is done to get rid of the compile warning: Reviewed-by: Chris Packham <judge.packham@gmail.com> ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
| * | | | watchdog: orion_wdt: take timeout value in msChris Packham2019-04-122-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic wdt_start API expects to be called with the timeout in milliseconds. Update the orion_wdt driver to accept a timeout in milliseconds and use the clock rate specified in the dts to convert the timeout to an appropriate value for the timer reload register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | watchdog: orion_wdt: support SPL usageChris Packham2019-04-121-3/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When run from the SPL the mvebu targets are using the hardware default offset for the SoC peripherals. devfdt_get_addr_size_index() understands how to deal with this via dm_get_translation_offset() so use this instead of fdtdec_get_addr_size_auto_noparent(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit (git 2.34.1) at 2025-04-22 10:41:08 +0000