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| * | fix: phy: marvell: cp110: sfi: update analog parameters according to latest ETPIgal Liberman2017-05-092-7/+121
| | | | | | | | | | | | | | | | | | | | | | | | Add SFI analog parameters initialization values according to latest ETP. Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: print comphy status even when it's disconnectedStefan Roese2017-05-091-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | since now the COMPHY can also be ignored, we must know the state of the COMPHY. we cannot assume anymore that a missing COMPHY is unconnected. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: phy: marvell: cp110: fix comphy lane 4 selection optionsStefan Roese2017-05-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comphy configuration is incorrect. Set the correct values for SGMII. In addition, remove xaui from the comment as it is not supported. Signed-off-by: Yoav Gvili <ygvili@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: cp110: add 5G XFI modeIgal Liberman2017-05-092-7/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the option to configure a comphy to 5G XFI mode. In order to configure the comphy to 5G XFI, update the comphy node in the device-tree: phy2 { phy-type = <PHY_TYPE_SFI>; phy-speed = <PHY_SPEED_5_15625G>; }; Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: phy: marvell: cp110: update comphy selector optionStefan Roese2017-05-091-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align PHY selectors register with Armada-CP-110 functional SPEC update all relevant device trees with this change. Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: phy: marvell: cp110: sata: update analog parameters according to latest ETPIgal Liberman2017-05-092-31/+336
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SATA analog parameters initialization values according to latest ETP. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: phy: marvell: cp110: fix the KR/SFI line 4 selectorStefan Roese2017-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following: 1. KR/SFI on lane #4 mux selector is 0x2 and not 0x1 2. Comment typo Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: add IGNORE COMPHY typeStefan Roese2017-05-093-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This type tells u-boot to preserve the COMPHY settings as is it is usefull in situations where the COMPHY was initialized by earlier firmware. Note that IGNORE is different from UNCONNECTED since setting UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX which is a desired behaviour Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: cp110: update utmi phy connection typeStefan Roese2017-05-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches. Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: cp110: add support for end point configurationStefan Roese2017-05-093-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The serdes was always configured in root complex mode. this patch add new entry in device tree (per serdes) which indicates whether the serdes is in end point mode. if so, it skips the root complex configuration. Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFIStefan Roese2017-05-092-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | Use correct naming as done in the latest Marvell U-Boot version as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: mvebu_ comphy: Update COMPHY sequence numberKonstantin Porotchkin2017-05-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use local static counter for maintaining the COMPHY chip-ID upon its initialization. The dev->seq originally used as the COMPHY chip-ID depends on the device tree scan order and produces wrong results that breaks the deficated PHYs init flow, which in turn breaks the USB support. Change-Id: I4e3f7ec36590a7f95dc94d9269a3c47fb708c4a9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: mvebu: pcie_dw: Allow probing empty PCIe slotsKonstantin Porotchkin2017-05-091-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows probing all PCIe nodes defined in DTS even if there no device connected to such node (no link). Without this fix the driver returns -ENODEV when the PCIe link is down. As result the pci_init function stops scanning bus on first empty PCIe slot and all devices located in higher numbered buses are not discovered. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | net: mvpp2: Add remove function that is called before the OS is startedStefan Roese2017-05-091-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a remove function to the mvpp2 ethernet driver which is called before the OS is started, doing: - Allocate the used buffers back from the buffer manager - Stop the BM activity Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2017-05-091-77/+200
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| * | drivers: i2c: davinci_i2c: Update davinci i2c driver to driver modelCooper Jr., Franklin2017-05-091-2/+90
| | | | | | | | | | | | | | | | | | | | | | | | Convert davinci i2c driver to driver model. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: davinci: Split functions into two parts for future DM supportCooper Jr., Franklin2017-05-091-75/+110
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The i2c driver will be converted to support device model. In preparation for that change split the various functions into two parts. This will allow device model specific driver to reuse the majority of the code from the non device model implementation. Also rename the probe function to probe_chip to better reflect its purpose. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* / dm: Update Simple Watchdog uclassMaxim Sloyko2017-05-091-11/+1
|/ | | | | | | | | | | - Remove "probe" function from sandbox wdt driver - Fix include order Fixes: 0753bc2d30d7 ("dm: Simple Watchdog uclass") Signed-off-by: Maxim Sloyko <maxims@google.com> [trini: Create as the delta between v1 (applied) and v2 (should have applied)]. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-05-085-0/+659
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| * sunxi: video: Add A64/H3/H5 HDMI driverJernej Skrabec2017-04-283-0/+648
| | | | | | | | | | | | | | | | | | This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: i2c: Add support for DM I2CJernej Skrabec2017-04-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for DM I2C on sunxi platform. It can coexist with old style sunxi I2C driver, because it is still used in SPL and by some SoCs. Because sunxi platform doesn't yet support DM clk, reset and pinctrl driver, workaround is needed to enable clocks and set resets and pinctrls. This is done by calling i2c_init_board() in board_init(). This means that CONFIG_I2Cx_ENABLE options needs to be correctly set in order to use needed I2C controller. Commit is based on the previous patch made by Philipp Tomsich Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: power: Compile sy8106a driver only during SPL buildJernej Skrabec2017-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | Driver for that regulator is used only in SPL and it uses old I2C interface. If we want to use DM I2C in U-Boot proper, compilation of this driver has to be limited only to SPL. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com2017-05-081-20/+19
| | | | | | | | | | | | | | | | | | Refactor SCU header to use consistent Mask & Shift values. Now, consistently, to read value from SCU register, mask needs to be applied before shift. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add support for Clocks needed by MACsmaxims@google.com2017-05-081-31/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add I2C Drivermaxims@google.com2017-05-084-0/+499
| | | | | | | | | | | | | | | | | | | | Add Device Model based I2C driver for ast2500/ast2400 SoCs. The driver is very limited, it only supports master mode and synchronous byte-by-byte reads/writes, no DMA or Pool Buffers. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | aspeed: Add P-Bus clock in ast2500 clock drivermaxims@google.com2017-05-081-0/+11
| | | | | | | | | | | | | | | | Add P-Bus Clock support to ast2500 clock driver. This is the clock used by I2C devices. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: AST2500 Pinctrl Drivermaxims@google.com2017-05-084-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver uses Generic Pinctrl framework and is compatible with the Linux driver for ast2500: it uses the same device tree configuration. Not all pins are supported by the driver at the moment, so it actually compatible with ast2400. In general, however, there are differences that in the future would be easier to maintain separately. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Refactor AST2500 RAM Driver and Sysreset Drivermaxims@google.com2017-05-081-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Reset Drivermaxims@google.com2017-05-083-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Make SCU lock/unlock functions part of SCU APImaxims@google.com2017-05-081-16/+2
| | | | | | | | | | | | | | | | | | Make functions for locking and unlocking SCU part of SCU API. Many drivers need to modify settings in SCU and thus need to unlock it first. This change makes it possible. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Watchdog Timer Drivermaxims@google.com2017-05-083-0/+137
| | | | | | | | | | | | | | | | | | This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: Simple Watchdog uclassmaxims@google.com2017-05-084-1/+169
| | | | | | | | | | | | | | | | | | | | This is a simple uclass for Watchdog Timers. It has four operations: start, restart, reset, stop. Drivers must implement start, restart and stop operations, while implementing reset is optional: It's default implementation expires watchdog timer in one clock tick. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rtc: Add DM support to ds1307Chris Packham2017-05-082-20/+196
| | | | | | | | | | | | | | | | Add an implementation of the ds1307 driver that uses the driver model i2c APIs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mtd: nand: Consolidate nand spl loaders implementationLadislav Michl2017-05-084-171/+110
| | | | | | | | | | | | | | | | | | | | nand_spl_load_image implementation was copied over into three different drivers and now with nand_spl_read_block used for ubispl situation gets even worse. For now use least intrusive solution and #include the same implementation to nand drivers. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
* | stm32f7: increase the max no of pin configuration to 70Vikas Manocha2017-05-081-1/+2
| | | | | | | | | | | | | | | | | | The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: sdram: correct sdram configuration as per micron sdramVikas Manocha2017-05-081-39/+16
| | | | | | | | | | | | | | | | | | | | | | | | Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same. Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: stm32f746-disco: read memory info from device treeVikas Manocha2017-05-081-1/+0
| | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: use stm32f7 gpio driver supporting driver modelVikas Manocha2017-05-082-41/+7
| | | | | | | | | | | | | | | | | | | | | | | | With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: gpio: Add driver for stm32f7 gpio controllerVikas Manocha2017-05-084-1/+182
| | | | | | | | | | | | | | | | | | | | This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com>
* | stm32f7: sdram: use sdram device tree node to configure sdram controllerVikas Manocha2017-05-081-53/+91
| | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: use clock driver to enable sdram controller clockVikas Manocha2017-05-081-0/+15
| | | | | | | | | | | | | | | | This patch also removes the sdram/fmc clock enable from board specific code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: dm: add driver model support for sdramVikas Manocha2017-05-081-0/+31
| | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: sdram: move sdram driver code to ram drivers areaVikas Manocha2017-05-083-0/+128
| | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | stm32f7: use clock driver to enable qspi controller clockVikas Manocha2017-05-081-1/+15
| | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* | arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocksUri Mashiach2017-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks during board_usb_exit to enable and disable clocks respectively. Modifications: * Enable USB clocks in the OMAP version of the function board_usb_init. * Disable USB clocks in the OMAP version of the function board_usb_cleanup. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | usb: host: xhci-omap: fix double weak board_usb_init functionsUri Mashiach2017-05-081-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A weak version of the function board_usb_init is implemented in: common/usb.c drivers/usb/host/xhci-omap.c To fix the double implementations: * Convert the board_usb_init function in drivers/usb/host/xhci-omap.c normal (not weak). * The function board_usb_init in drivers/usb/host/xhci-omap.c calls to the weak function omap_xhci_board_usb_init. * Rename board version of the function board_usb_init to omap_xhci_board_usb_init. Done only for boards that defines CONFIG_USB_XHCI_OMAP. To achieve the same flexibility with the function board_usb_cleanup: * Add a normal (not weak) implementation of the function board_usb_cleanup in drivers/usb/host/xhci-omap.c * The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls to the weak function omap_xhci_board_usb_cleanup. * Rename board version of the function board_usb_cleanup to omap_xhci_board_usb_cleanup. Done only for boards that defines CONFIG_USB_XHCI_OMAP. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
* | arm: usb: dra7xx: xHCI registers based on USB port indexUri Mashiach2017-05-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the determination of the base address of xHCI registers of DRA7XX targets. Before the commit: by the target. After the commit: by the USB port index. Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* | drivers: spi: Remove duplicate .probe methodSuniel Mahesh2017-05-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | .probe method has been assigned twice when declaring a driver with U_BOOT_DRIVER(). Removed one of them. Here is the last commit which had the duplicate entry: "spi: omap3: Convert to driver model" (sha1: 77b8d04854f486741471ad02b93b473b5b3d72f8) Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | zynq: spi: Honour the activation / deactivation delayMoritz Fischer2017-05-031-0/+24
| | | | | | | | | | | | | | | | | | This is not currently implemented. Add support for this so that the Chrome OS EC can be used reliably. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | spi: atmel: check GPIO validity before using cs_gpiosWenyou Yang2017-05-031-0/+9
| | | | | | | | | | | | | | Before using the cs_gpio, check if the GPIO is valid or not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit (git 2.34.1) at 2024-09-30 18:14:52 +0000