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* arm: a37xx: pci: Fix configuring PCIe resourcesPali Rohár2021-06-041-1/+157
| | | | | | | | | | | | | | | | | | | | | | | The `ranges` DT property of the PCIe node is currently ignored by Aardvark driver - all entries are used as transparent PCIe MEM, despite some of them being defined for IO in DT. This is because the driver does not setup PCIe outbound windows and thus a default configuration is used. This can cause an external abort on CPU when a device driver tries to access non-MEM space. Setup the PCIe windows according to the `ranges` property for all non-MEM resources (currently only IO) and also non-transparent MEM resources. Because Linux expects that bootloader does not setup Aardvark PCIe windows, disable them before booting Linux. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Fix DT compatible string to Linux' DT compatiblePali Rohár2021-06-041-1/+1
| | | | | | | | | | Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Disable bus mastering when unloading driverPali Rohár2021-06-041-0/+6
| | | | | | | | | | | | | | | | | | Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Don't put link into LTSSM Recovery state during probePali Rohár2021-06-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: pci: pcie_dw_common: fix Werror compilation errorGreen Wan2021-05-311-25/+29
| | | | | | | | Fix compilation error when Werror is turned on. The warning could possible break some CI builds. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* board: sifive: add HiFive Unmatched board supportGreen Wan2021-05-311-1/+1
| | | | | | | | Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* drivers: pci: add pcie support for fu740Green Wan2021-05-313-0/+518
| | | | | | | | | | | | | | Add pcie driver for SiFive fu740, the driver depends on fu740 gpio, clk and reset driver to do init. Force running at Gen1 for better capatible enumeration. Several devices are tested: a) M.2 NVMe SSD b) USB-to-PCI adapter c) Ethernet adapter (E1000 compatible) Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
* drivers: ram: sifive: rename fu540_ddr and add fu740 supportGreen Wan2021-05-313-49/+50
| | | | | | | Rename fu540_ddr.c to sifive_ddr.c and add fu740 support Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* drivers: clk: add fu740 supportGreen Wan2021-05-319-754/+1287
| | | | | | | Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan <green.wan@sifive.com>
* reset: stm32: Fix bank and offset computationPatrice Chotard2021-05-281-4/+4
| | | | | | | | | | | | BITS_PER_LONG is used to represent register's size which is 32. But when compiled on arch64, BITS_PER_LONG is then equal to 64. Fix bank and offset computation to make it work on arch32 and arch64 and ensure that register's size is always equal to 32. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* dfu: dfu_mtd: remove the mtd_block_op error when mtd_lock is not supportedPatrick Delaunay2021-05-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix the result of DFU_OP_WRITE operation in mtd_block_op function when mtd_lock is not supported (-EOPNOTSUPP) to avoid DFU stack error on the DFU manifestation of the MTD device, when dfu_flush_medium_mtd is called. Without this patch, dfu-util failed on dfuERROR state at the end of the write operation on the alternate even if MTD write opeartion is correctly performed. $> dfu-util -a 3 -D test.bin .... DFU mode device DFU version 0110 Device returned transfer size 4096 Copying data from PC to DFU device .... Download [=========================] 100% 225469 bytes Download done. state(10) = dfuERROR, status(14) = Something went wrong, but the device does not know what it was Done! Fixes: 65f3fc18fc1e ("dfu_mtd: Add provision to unlock mtd device") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
* Merge tag 'ti-v2021.07-rc4' of ↵Tom Rini2021-05-272-0/+3
|\ | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Fix reset for AM64 platforms - Enable networking PHY driver for AM64 - Fix default R5F cluster setting in J7
| * firmware: ti_sci: Update ti_sci_msg_req_reboot to include domainDave Gerlach2021-05-272-0/+3
| | | | | | | | | | | | | | | | | | | | | | The ti_sci_msg_req_reboot message payload has been extended to include a domain field, but for the purposes of u-boot this should be zero to reset the entire SoC as it did before. Include domain for completeness and set to zero to ensure proper operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | pinctrl: single: Fix probe failure getting register area sizeVignesh Raghavendra2021-05-261-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If reg property of pinctrl-single node requires address translation then probe fails with following message: single-pinctrl pinctrl@4301c000: failed to get base register size This is because driver uses dev_read_addr_size() to get size which also tries to fetch untranslated addr and fails. Fix this by using dev_read_addr_size_index() which takes care of address translation and also makes following dev_read_addr() call redundant. This fixes Ethernet failures on TI's AM654 based EVMs due to lack of pinmux configuration. Fixes: 9fd8a430f3 ("pinctrl: single: get register area size by device API") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | net: Remove ne2000 driverTom Rini2021-05-256-1576/+0
|/ | | | | | | With the last user of this driver removed, remove the driver. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ata: ahci: fix ahci_link_up() type mismatch for LTOMarek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | | | | When building highbank_defconfig with LTO, the compiler complains about type mismatch of function ahci_link_up(). The third parameter of this function is of type u8 in drivers/ata/ahci.c, but of type int in board/highbank/ahci.c. There is no reason in using u8, and the code using this function actually passes an int variable into the function (so it is implicitly converted to u8). Change the type of this parameter to int in drivers/ata/ahci.c. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: fix LTO for apf27Marek Behún2021-05-241-1/+1
| | | | | | | | When apf27_defconfig is built with LTO, linking complains about undefined reference to `nand_boot`. This is because it is referenced from inline assembly. Make it visible. Signed-off-by: Marek Behún <marek.behun@nic.cz>
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-2411-14/+14
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* regmap: fix a serious pointer casting bugMarek Behún2021-05-241-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a serious bug in regmap_read() and regmap_write() functions where an uint pointer is cast to (void *) which is then cast to (u8 *), (u16 *), (u32 *) or (u64 *), depending on register width of the map. For example given a regmap with 16-bit register width the code int val = 0x12340000; regmap_read(map, 0, &val); only changes the lower 16 bits of val on little-endian machines. The upper 16 bits will remain 0x1234. Nobody noticed this probably because this bug can be triggered with regmap_write() only on big-endian architectures (which are not used by many people anymore), and on little endian this bug has consequences only if register width is 8 or 16 bits and also the memory place to which regmap_read() should store it's result has non-zero upper bits, which it seems doesn't happen anywhere in U-Boot normally. CI managed to trigger this bug in unit test of dm_test_devm_regmap_field when compiled for sandbox_defconfig using LTO. Fix this by utilizing an union { u8; u16; u32; u64; } and reading data into this union / writing data from this union. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Pratyush Yadav <p.yadav@ti.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini2021-05-2325-377/+452
|\ | | | | | | - Various clk/pinctrl updates to re-sync with Linux and other fixes
| * pinctrl: renesas: Implement unlock register masksMarek Vasut2021-05-212-21/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * pinctrl: renesas: Fix R-Car Gen2 help textMarek Vasut2021-05-211-5/+5
| | | | | | | | | | | | | | | | The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * pinctrl: renesas: Deduplicate KconfigMarek Vasut2021-05-211-69/+5
| | | | | | | | | | | | | | | | The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()Marek Vasut2021-05-211-7/+6
| | | | | | | | | | | | | | Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut2021-05-211-43/+43
| | | | | | | | | | | | | | | | | | Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham2021-05-213-45/+65
| | | | | | | | | | | | | | | | | | Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Introduce enum clk_reg_layoutHai Pham2021-05-211-0/+6
| | | | | | | | | | | | | | | | From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham2021-05-214-6/+8
| | | | | | | | | | | | | | | | | | CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Make reset controller modemr register offset configurableMarek Vasut2021-05-2120-5/+21
| | | | | | | | | | | | | | | | | | | | | | The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Add support for RPCD2 clockHai Pham2021-05-212-5/+17
| | | | | | | | | | | | | | | | | | This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham2021-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham2021-05-211-1/+1
| | | | | | | | | | | | | | | | RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2021-05-212-0/+18
| | | | | | | | | | | | | | | | Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut2021-05-217-163/+212
| | | | | | | | | | | | | | Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut2021-05-215-9/+6
| | | | | | | | | | | | | | Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * clk: renesas: Synchronize RZ/G2 tables with Linux 5.12Marek Vasut2021-05-213-5/+26
| | | | | | | | | | | | | | Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | net: mvpp2: add explicit sgmii-2500 supportMarcin Wojtas2021-05-201-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: mvpp2: allow MDIO registration for fixed linksStefan Chulski2021-05-201-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | net: mvpp2: fix missing switch case breakBen Peled2021-05-201-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REGBen Peled2021-05-201-3/+0
| | | | | | | | | | | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: mvpp2: AN Bypass in 1000 and 2500 basex modeBen Peled2021-05-201-2/+4
| | | | | | | | | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | net: mvpp2: Fix 2.5G GMII_SPEED configurationsStefan Chulski2021-05-201-1/+2
| | | | | | | | | | | | | | | | | | GMII_SPEED should be enabled for 2.5G speed Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Yan Markman <ymarkman@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | net: mvpp2: remove redundant SMI address configurationMarcin Wojtas2021-05-201-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: mvpp2: add 1000BaseX and 2500BaseX ppv2 supportStefan Chulski2021-05-201-5/+112
| | | | | | | | | | | | Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: mvpp2: add CP115 port1 10G/5G SFI supportStefan Chulski2021-05-201-58/+17
|/ | | | | | | | | | | 1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch '2021-05-17-assorted-fixes'Tom Rini2021-05-181-2/+3
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| * psci: rename psci_features functionIgor Opaniuk2021-05-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/psci_features/request_psci_features/g for the case when both ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these compilation issues: drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features' 69 | static int psci_features(u32 psci_func_id) | ^~~~~~~~~~~~~ In file included from drivers/firmware/psci.c:23: ./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here 548 | s32 psci_features(u32 function_id, u32 psci_fid); | ^~~~~~~~~~~~~ Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Fixes: b7135b034f ("psci: add features/reset2 support") Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-05-181-1/+1
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| * riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-05-172-17/+87
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya) - Sync Armada 8k MMU setup with Marvell version (misc Marvell authors) - spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors) - mvebu: x530: Reduce SPL image size (Stefan) - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
generated by cgit (git 2.34.1) at 2024-06-03 06:42:16 +0000