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| * | | mmc: zynq_sdhci: Move macro to the topMichal Simek2020-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just group macros below headers. Other patches will be using this location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: Define timing macro'sAshok Reddy Soma2020-10-271-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | | Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma2020-10-272-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | | spi: zynq_qspi: Add function descriptionAshok Reddy Soma2020-10-271-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect. Fix zqspi to priv in function descriptions. Change the description of priv as pointer to zynq_qspi_priv structure. Fix other function descriptions to kernel-doc style. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | mtd: spi: Fix incorrect indentationMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use tabs to be aligned with the rest of the code. Fixes: 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board KconfigMichal Simek2020-10-271-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to have ZYNQ specific Kconfig macro in generic location to be visible for all other SoCs. That's why move it to Xilinx common location to be visible only for us. Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to disable it or enable. This has connection to code which is reading the whole content of i2c and also work with the rest of date not just with MAC address. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | spi: zynq_qspi: Use clk subsystem to get reference qspi clkT Karthik Reddy2020-10-271-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | spi: zynq_spi: Use clk subsystem to get reference spi clkT Karthik Reddy2020-10-271-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | serial: pl01x: Add error value checkingMichal Simek2020-10-271-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There also a need to check return values to make sure that clocks were enabled and setup properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add support for getting node from aliasesMichal Simek2020-10-271-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for getting a node/property from aliases. The similar functionality is provided for chosen node and this implemenatation is copy of it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | spi: xilinx_spi: remove unused local variableT Karthik Reddy2020-10-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused variable 'count' which is causing warning while compilation. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | mailbox: zynqmp: Extend timeout for getting observation bitMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of fpga loading (which can be huge) 100ms is not enough. That's why extend timeout 10 times to wait maximum 1s to get ACK back. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is calledMichal Simek2020-10-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't know reason but in regular flow addr_hi/low are swapped in ATF. It means when fpga load is done from EL3 there is a need to swap it for PMUFW to load bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | spi: xilinx_spi: Remove unused variableMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused variable: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable] 254 | u32 reg, count, timeout; | ^~~~~~~ Fixes: 0c0de58f7b30 ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-296-92/+512
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * | | dm: pci: fsl: Correct the workaround of erratum A-007815Hou Zhiqiang2020-10-232-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | gpio: mpc8xxx: support fsl-layerscape platformhui.song2020-10-231-21/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the MPC8XXX gpio driver to support the fsl-layerscape. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2020-10-232-0/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: move pci node search in a common functionLaurentiu Tudor2020-10-231-42/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: move per-pci device fdt fixup in a functionLaurentiu Tudor2020-10-231-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pci device related fdt fixup in a function in order to re-use it in a following patch. While at it, improve the error handling. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | | drivers: mux: mmio-based syscon mux controllerJean-Jacques Hiblot2020-10-283-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for mmio-based syscon multiplexers controlled by bitfields in a syscon register range. This is heavily based on the linux mmio-mux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* | | | dm: board: complete the initialization of the muxes in initr_dm()Jean-Jacques Hiblot2020-10-281-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will probe the multiplexer devices that have a "u-boot,mux-autoprobe" property. As a consequence they will be put in their idle state. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* | | | drivers: Add a new framework for multiplexer devicesJean-Jacques Hiblot2020-10-285-0/+332
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | rtc: provide an emulated RTCHeinrich Schuchardt2020-10-273-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a board without hardware clock this software real time clock can be used. The build time is used to initialize the RTC. So you will have to adjust the time either manually using the 'date' command or use the 'sntp' to update the RTC with the time from a network time server. See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU ticks. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | | Merge tag 'video-for-2021.01-rc1' of ↵Tom Rini2020-10-261-1/+8
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-video - disable CONFIG_VIDEO to remove DM conversion warnings for boards: at91sam9, eb_cpu5282, ls1021aqds, ls1021atwr, mx23evk, mx6sxsabresd, mx7dsabresd, nokia_rx51, picosam9g45, sansa_fuze_plus, xfi3
| * | | | nokia_rx51: disable obsolete VIDEO configAnatolij Gustschin2020-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable VIDEO config to fix DM_VIDEO conversion deadline warning. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | | eb_cpu5282: fix CONFIG_DM_VIDEO build warningsAnatolij Gustschin2020-10-261-0/+7
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_VIDEO dependency to fix board removal warnings. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Jens Scharsig <esw@bus-elektronik.de>
* | | | riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson2020-10-262-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: Move Andes PLMT driver to drivers/timerSean Anderson2020-10-263-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | clk: kendryte: no need to check argument of free()Heinrich Schuchardt2020-10-261-2/+1
|/ / / | | | | | | | | | | | | | | | | | | free() checks if its argument is NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | | phy: nop-phy: add clk bulkPeng Fan2020-10-231-0/+35
| | | | | | | | | | | | | | | | | | Add clk bulk for nop-phy driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | i2c: i2c-gpio: Convert to use APIs which support live DTPatrick Delaunay2020-10-231-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | power: regulator: gpio-regulator: Convert to use APIs which support live DTPatrick Delaunay2020-10-231-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | power: regulator: gpio-regulator: protect count valuePatrick Delaunay2020-10-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the size of states_array to avoid overflow for dev_pdata->voltages[j] and dev_pdata->states[j]. As the size of array is GPIO_REGULATOR_MAX_STATES, the size of states_array is limited by GPIO_REGULATOR_MAX_STATES * 2 = 4 instead of 8 previously. The value of the "count" variable is limited by the third parameter of fdtdec_get_int_array_count. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Revert "serial: serial_xen: print U-Boot banner and others"Tom Rini2020-10-231-0/+2
| | | | | | | | | | | | | | | | | | This reverts commit 18426bf02217de2e9bb2b41eaa74d769892c55ef. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Revert "serial: serial_xen: add DEBUG_UART support"Tom Rini2020-10-232-31/+3
| | | | | | | | | | | | | | | | | | This reverts commit 82e21b391bd315f6fe0e0b79326af8a141e9cca7. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2020-10-221-251/+206
|\ \ \ | |/ / |/| | | | | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * | net: sun8i-emac: Lower MDIO frequencyAndre Przywara2020-10-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i-emac: Make internal PHY handling more robustAndre Przywara2020-10-211-32/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Simplify and fix error handling for RXAndre Przywara2020-10-211-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix MAC soft resetAndre Przywara2020-10-211-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix overlong linesAndre Przywara2020-10-211-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Wrap and simplify cache maintenance operationsAndre Przywara2020-10-211-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Drop unneeded cache invalidation before sendingAndre Przywara2020-10-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Reduce cache maintenance on TX descriptor initAndre Przywara2020-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Improve cache maintenance on RX descriptor initAndre Przywara2020-10-211-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Name magic bits and simplify read-modify-write callsAndre Przywara2020-10-211-52/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Remove pointless wrapper functionsAndre Przywara2020-10-211-46/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2025-09-30 02:11:22 +0000