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| * | x86: sound: Correct error handlingSimon Glass2020-11-062-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | A few functions have changed to return pin numbers or I2C addresses. The error checking for some of the callers is therefore wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-055-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cros_ec: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-053-6/+6
| |/ | | | | | | | | | | | | | | Fix the dtoc warning in these file by using a driver name that matches the compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20201105' of ↵Tom Rini2020-11-059-12/+377
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx for 2021.1 --------------------- - new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM - converted doc to reST - fixes for verdin-imx8mm (Toradex) - fixes for i.MX thermal driver - mx7ulp: Align the PLL_USB frequency - mx53: primary/secondary bmode Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
| * sysreset: Add poweroff-gpio driverSebastian Reichel2020-11-013-0/+100
| | | | | | | | | | | | | | | | Add GPIO poweroff driver, which is based on the Linux driver and uses the same DT binding. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * rtc: m41t62: add oscillator fail bit reset supportSebastian Reichel2020-11-011-0/+50
| | | | | | | | | | | | | | | | In case of empty battery or glitches the oscillator fail bit might be set. This will reset the bit in the reset routine. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * rtc: m41t62: reset SQW in m41t62_rtc_resetSebastian Reichel2020-11-011-6/+83
| | | | | | | | | | | | | | This takes care of resetting the 32kHz square wave, which is used by some boards as clock source for the SoC. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * bootcount: add a DM SPI flash backing store for bootcountSebastian Reichel2020-11-013-0/+136
| | | | | | | | | | | | | | This driver allows to use SPI flash as backing store for boot counter values with DM enabled. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * watchdog: Hide WATCHDOG_RESET_DISABLEMichael Walle2020-11-011-6/+7
| | | | | | | | | | | | | | | | | | This option is only supported by the IMX watchdog and seems to be similar to CONFIG_WATCHDOG. Move it below the IMX watchdog and make it dependent on IMX_WATCHDOG. Signed-off-by: Michael Walle <michael@walle.cc>
| * thermal: imx_tmu: fix missing includeTim Harvey2020-11-011-0/+1
| | | | | | | | | | | | | | | | commit c05ed00afb dropped linux/delay.h from common header add linux/delay.h to avoid compile warning here Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | Merge tag 'efi-2020-01-rc2-2' of ↵Tom Rini2020-11-017-78/+163
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc2 (2) The series contains the following enhancements * preparatory patches for UEFI capsule updates * initialization of the emulated RTC using an environment variable and a bug fix * If DisconnectController() is called for a child controller that is the only child of the driver, the driver must be disconnected.
| * dfu: add dfu_write_by_alt()AKASHI Takahiro2020-10-301-0/+47
| | | | | | | | | | | | | | | | | | | | | | This function is a variant of dfu_write_by_name() and takes a DFU alt setting number for dfu configuration. It will be utilised to implement UEFI capsule management protocol for raw image in a later commit. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * dfu: export dfu_listAKASHI Takahiro2020-10-301-1/+1
| | | | | | | | | | | | | | | | This variable will be utilized to enumerate all dfu entities for UEFI capsule firmware update in a later commit. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * common: update: add a generic interface for FIT imageAKASHI Takahiro2020-10-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | The main purpose of this patch is to separate a generic interface for updating firmware using DFU drivers from "auto-update" via tftp. This function will also be used in implementing UEFI capsule update in a later commit. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * dfu: modify an argument type for an addressAKASHI Takahiro2020-10-301-3/+3
| | | | | | | | | | | | | | | | | | The range of an addressable pointer can go beyond 'integer'. So change the argument type to a void pointer. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * dfu: rename dfu_tftp_write() to dfu_write_by_name()AKASHI Takahiro2020-10-303-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | This function is essentially independent from tftp, and will also be utilised in implementing UEFI capsule update in a later commit. So just give it a more generic name. In addition, a new configuration option, CONFIG_DFU_WRITE_ALT, was introduced so that the file will be compiled with different options, particularly one added in a later commit. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * rtc: initialize emulated RTC from environment variableHeinrich Schuchardt2020-10-302-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now the emulated RTC is initialized using the U-Boot build time. With this patch the environment variable 'rtc_emul_epoch' can be used to provide a better initial time. The variable is a decimal string with the number of seconds since 1970-01-01. Here is an example where the RTC had not been probed yet: => setenv rtc_emul_epoch 1610109000 => date Date: 2021-01-08 (Friday) Time: 12:30:00 If the variable does not exist, the U-Boot build time is used as fallback. The environment variable may be set when shutting down the operating system if the U-Boot environment is exposed to the OS (cf. ENV_IS_IN_FAT and ENV_IS_IN_EXT4). Suggested-by: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * rtc: use probe() to initialize emulated RTCHeinrich Schuchardt2020-10-301-6/+12
| | | | | | | | | | | | | | | | | | Currently the emulated RTC is initialized in the emul_rtc_get() get function. This does not match the design of the driver model. Move the initialization of the emulated RTC to the probe() function. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini2020-10-305-2/+57
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
| * | video: rockchip: Support 4K resolution for rk3288, HDMIJagan Teki2020-10-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like, rk3399 the rk3288 also supports 4K resolution. So, enable it for rk3288 with HDMI platforms. Right now, rockchip video drivers are supporting for rk3288, rk3399 SoC families, so mark the 4K resolution by default if it's an HDMI video out. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | video: rockchip: Add missing dpcd_write() call to link_train_ce()Alper Nebi Yasak2020-10-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found this by comparing it to the coreboot driver, a form of this call was introduced there in their commit b9a7877568cf ("rockchip/*: refactor edp driver"). This is copy-pasted from U-Boot's link_train_cr() slightly above it. Without this on a gru-kevin chromebook, I have: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB channel eq failed, ret=-5 link train failed! rk_vop_probe() Device failed: ret=-5 With this, it looks like training succeeds: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 config video failed rk_vop_probe() Device failed: ret=-110 The "config video failed" error also goes away when I disable higher log levels, and it claims to have successfully probed the device. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2020-10-302-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell2020-10-301-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge tag 'dm-pull-30oct20' of ↵Tom Rini2020-10-3021-111/+165
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
| * | | dm: Use driver_info index instead of pointerSimon Glass2020-10-294-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Take advantage of the of-platdata parent supportSimon Glass2020-10-291-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass2020-10-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Convert #ifdef to if() in root.cSimon Glass2020-10-291-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert a few conditions to use compile-time checks to reduce the number of build paths. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Add a test for of-platdata parent informationSimon Glass2020-10-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple test that we can obtain the correct parent for an I2C device. This requires updating the driver names to match the compatible strings, adding them to the devicetree and enabling a few options. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Support parent devices with of-platdataSimon Glass2020-10-291-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present of-platdata does not provide parent information. But this is useful for I2C devices, for example, since it allows them to determine which bus they are on. Add support for setting the parent correctly, by storing the parent driver_info index in dtoc and reading this in lists_bind_drivers(). This needs multiple passes since we must process children after their parents already have been bound. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Fix up building for of-platdataSimon Glass2020-10-293-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no devicetree with of-platdata. Update a few uclasses to allow them to be built for sandbox_spl. Also drop the i2c-gpio from SPL to avoid build errors, since it does not support of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Use an allocated array for run-time device infoSimon Glass2020-10-293-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we update the driver_info struct with a pointer to the device that it created (i.e. caused to be bound). This works fine when U-Boot SPL is stored in read-write memory. But on some platforms, such as Intel Apollo Lake, it is not possible to update the data memory. In any case, it is bad form to put this information in a structure that is in the data region, since it expands the size of the binary. Create a new driver_rt structure which holds runtime information about drivers. Update the code to store the device pointer in this instead. Also update the test check that this works. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Add a test for of-platdata phandlesSimon Glass2020-10-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a test in dtoc for this feature, but not one in U-Boot itself. Add a simple test that checks that the information comes through correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Add a check that all devices have a dev valueSimon Glass2020-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With of-platdata, the driver_info struct is updated with the device pointer when it is bound. This makes it easy for a device to be found by its driver info with the device_get_by_driver_info() function. Add a test that all devices (except the root device) have such an entry. Fix a bug that the function does not set *devp to NULL on failure, which the documentation asserts. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Drop of-platdata pytestSimon Glass2020-10-291-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have a C version of this test, drop the Python implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Allow dm_warn() to be used in SPLSimon Glass2020-10-292-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this option is disabled in SPL, meaning that warnings are not displayed. It is sometimes useful to see warnings in SPL for debugging purposes. Add a new Kconfig option to permit this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Drop ad-hoc device declarations in SPLSimon Glass2020-10-292-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since sandbox's SPL is build with of-platadata, we should not use U_BOOT_DEVICE() declarations as well. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Avoid using #ifdef for CONFIG_OF_LIVESimon Glass2020-10-292-19/+10
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | At present this option results in a number of #ifdefs due to the presence or absence of the global_data of_root member. Add a few macros to global_data.h to work around this. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-293-1248/+205
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
| * | | mtd: nand: pxa3xx: enable NAND controller if the SoC needs itShmuel Hazan2020-10-292-10/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable NAND controller if the SoC needs it"). This commit adds support for the Armada 8040 nand controller. The kernel commit says this: Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | mtd: pxa3xx_nand: remove dead codeBaruch Siach2020-10-291-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kfree() call is unreachable, and is not needed. Remove this call and the fail_disable_clk label. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | mtd: pxa3xx_nand: port to use driver modelShmuel Hazan2020-10-292-63/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic DT code to find the device compatible property for us. This makes the driver look more like other current drivers. It also make it easier to add support for other variants like Armada 8K in a future commit. Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: update mode parameter for pcie power on callsIgal Liberman2020-10-291-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It helps ATF to determine who called power on function (U-boot/Linux). The corresponding ATF code was added in this commit: mvebu: cp110: avoid pcie power on/off sequence when called from Linux https://github.com/ARM-software/arm-trusted-firmware/commit/55df84f974ea37abbb4f93f000f101f70cda5303 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: let the firmware configure comphy for PCIeGrzegorz Jaszczyk2020-10-291-439/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the comphy initialization for PCIe with appropriate SMC call, so the firmware will perform appropriate comphy initialization. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: let the firmware configure the comphyGrzegorz Jaszczyk2020-10-291-727/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all comphy initialization with appropriate smc calls. It will result with triggering synchronous exception that is handled by Secure Monitor code in EL3. Then the Secure Monitor code will dispatch each smc call (by parsing the smc function identifier) and triggers appropriate comphy initialization. This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI interfaces. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | | Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-2911-66/+524
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * | | mmc: zynq_sdhci: Extend UHS timings till hs200Ashok Reddy Soma2020-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the condition to set UHS timings for speeds upto HS200. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma2020-10-271-4/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma2020-10-271-5/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define and use functions for setting input and output tapdelays based on clk phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek2020-10-271-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define input and output clock phase delays with pre-defined values. Define arasan_sdhci_clk_data type structure and add it to priv structure and store these clock phase delays in it. Read input and output clock phase delays from dt. If these values are not passed through dt, use pre-defined values. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
generated by cgit (git 2.34.1) at 2025-09-29 13:29:29 +0000