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| * | remoproc: stm32: migrate trace to log macroPatrick Delaunay2021-01-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define LOG_CATEGORY and remove unneeded pr_fmt macro with the dev macro as dev->name is displayed and CONFIG_LOGF_FUNC can be activated for log macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | gpio: stm32-gpio: migrate trace to dev and log macroPatrick Delaunay2021-01-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change debug to dev_dbg macro and define LOG_CATEGORY. Remove dev->name as it is already displayed by dev macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | pinctrl: stm32: migrate trace to log macroPatrick Delaunay2021-01-131-14/+16
| |/ | | | | | | | | | | | | | | | | | | Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini2021-01-137-5/+307
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
| * adc: meson-saradc: use correct printf codeHeinrich Schuchardt2021-01-111-1/+1
| | | | | | | | | | | | | | | | For printing unsigned int we have to use %u not %d. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * adc: meson-saradc: skip hardware init only if ADC is enabledMarek Szyprowski2021-01-111-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | The driver skips hardware initialization if it is already configured by the earlier bootloader stage (BL30). Skip the initialization only if the hardware is really initialized and enabled. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * adc: meson-saradc: add G12A variantMarek Szyprowski2021-01-111-0/+2
| | | | | | | | | | | | | | | | | | | | Add support for the SARADC variant found on the G12A SoCs family. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * clk: meson: add minimal driver for g12a-ao clocksMarek Szyprowski2021-01-112-0/+84
| | | | | | | | | | | | | | | | | | | | | | Add minimal driver AO clocks on meson G12A family. Only ADC related clocks are supported. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * video: add TDO tl070wsh30 panel driverNeil Armstrong2021-01-113-0/+165
| | | | | | | | | | | | | | | | | | This adds support for the TDO TL070WSH30 TFT-LCD panel module. The panel has a 1024×600 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI interface to the host, a built-in LED backlight and touch controller. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * power: domain: meson-ee-pwrc: add support for the Meson AXG SoCsNeil Armstrong2021-01-111-0/+26
| | | | | | | | | | | | This syncs with the linux meson-ee-pwrc driver from Linux 5.10-rc1. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * power: domain: meson-ee-pwrc: add support for the Meson GX SoCsNeil Armstrong2021-01-111-2/+24
| | | | | | | | | | | | This syncs with the linux meson-ee-pwrc driver from Linux 5.10-rc1. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | remoteproc: ti_k3_arm64: Program CNTFID0 register in GTCNishanth Menon2021-01-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8's generic timer[1] picks up it's graycode from GTC. However, the frequency of the GTC is supposed to be programmed in CNTFID0[2] register prior to enabling the GTC in CNTCR[3] register. In K3 architecture, GTC provides a central time to many parts of the SoC including graycode to the generic timer in the ARMv8 subsystem. However, due to the central nature and the need to enable the counter early in the boot process, the R5 based u-boot enables GTC and programs it's frequency based on central needs of the system. This may not be a constant 200MHz based on the system. The bootloader is supposed to program the FID0 register with the correct frequency it has sourced for GTC from the central system controller OR from PLLs as appropriate, and TF-A is supposed[4] to use that as the frequency for it's local timer. Currently we are programming just the CNTCR[3] register to enable the GTC, however we dont let TF-A know the frequency that GTC is actually running at. A mismatch in programmed frequency and what we program for generic timer will, as we can imagine, all kind of weird mayhem. So, program the CNTFID0 register with the clock frequency. Note: assigned-clock-rates should have set the clock frequency, so the only operation we need to explicitly do is to retrieve the frequency and program it in FID0 register. Since the valid in K3 for GTC clock frequencies are < U32_MAX, we can just cast the ulong and continue. [1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary [2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0 [3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr [4] https://github.com/ARM-software/arm-trusted-firmware/commit/6a22d9ea3c7fa28d053d3ba264b49b7396a86f9e Signed-off-by: Nishanth Menon <nm@ti.com>
* | video: omap: move drivers to 'ti' directoryDario Binacchi2021-01-1210-7/+20
| | | | | | | | | | | | | | Add drivers/video/ti/ folder and move all TI's code in this folder for better maintenance. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | video: omap: split the legacy code from the DM codeDario Binacchi2021-01-127-374/+468
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The schedule for deprecating the features of the pre-driver-model puts 2019.17 as the deadline for the video subsystem. Furthermore, the latest patches applied to the am335x-fb.c module have decreased the amount of code shared with the pre-driver-model implementation. Splitting the two implementations into two modules improves the readability of the code and will make it easier to drop the pre-driver-model code. I have not created a header file with the data structures and the constants for accessing the LCD controller registers, but I preferred to keep them inside the two c modules. This is a code replication until the pre-driver-model version is dropped. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | video: omap: set LCD clock rate through DM APIDario Binacchi2021-01-121-26/+103
| | | | | | | | | | | | | | | | | | | | | | The patch configures the display DPLL using the functions provided by the driver model API for the clock. The device tree contains everything needed to get the DPLL clock. The round rate function developed for calculating the DPLL multiplier and divisor and the platform routines for accessing the DPLL registers are removed from the LCD driver code because they are implemented inside the DPLL clock driver. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | video: omap: add panel driverDario Binacchi2021-01-125-150/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous version of am335x-fb.c contained the functionalities of two drivers that this patch has split. It was a video type driver that used the same registration compatible string that now registers a panel type driver. The proof of this is that two compatible strings were referred to within the same driver. There are now two drivers, each with its own compatible string, functions and API. Furthermore, the panel driver, in addition to decoding the display timings, is now also able to manage the backlight. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: core: add a function to decode display timingsDario Binacchi2021-01-121-0/+6
| | | | | | | | | | | | | | | | The patch adds a function to get display timings from the device tree node attached to the device. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | bus: ti: am33xx: add pwm subsystem driverDario Binacchi2021-01-123-0/+28
| | | | | | | | | | | | | | | | | | | | | | The TI PWMSS driver is a simple bus driver for providing clock and power management for the PWM peripherals on TI AM33xx SoCs, namely eCAP, eHRPWM and eQEP. For DT binding details see Linux doc: - Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | pwm: ti: am33xx: add enhanced pwm driverDario Binacchi2021-01-123-0/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | Enhanced high resolution PWM module (EHRPWM) hardware can be used to generate PWM output over 2 channels. This commit adds PWM driver support for EHRPWM device present on AM33XX SOC. The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | omap: timer: fix the rate settingDario Binacchi2021-01-121-3/+3
| | | | | | | | | | | | | | The prescaler (PTV) setting must be taken into account even when the timer input clock frequency has been set. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | fdt: translate address if #size-cells = <0>Dario Binacchi2021-01-125-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __of_translate_address routine translates an address from the device tree into a CPU physical address. A note in the description of the routine explains that the crossing of any level with since inherited from IBM. This does not happen for Texas Instruments, or at least for the beaglebone device tree. Without this patch, in fact, the translation into physical addresses of the registers contained in the am33xx-clocks.dtsi nodes would not be possible. They all have a parent with #size-cells = <0>. The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation possible even in the case of crossing levels with #size-cells = <0>. The patch acts conservatively on address translation, except for removing a check within the of_translate_one function in the drivers/core/of_addr.c file: + ranges = of_get_property(parent, rprop, &rlen); - if (ranges == NULL && !of_empty_ranges_quirk(parent)) { - debug("no ranges; cannot translate\n"); - return 1; - } if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); debug("empty ranges; 1:1 translation\n"); There are two reasons: 1 The function of_empty_ranges_quirk always returns false, invalidating the following if statement in case of null ranges. Therefore one of the two checks is useless. 2 The implementation of the of_translate_one function found in the common/fdt_support.c file has removed this check while keeping the one about the 1:1 translation. The patch adds a test and modifies a check for the correctness of an address in the case of enabling translation also for zero size cells. The added test checks translations of addresses generated by nodes of a device tree similar to those you can find in the files am33xx.dtsi and am33xx-clocks.dtsi for which the patch was created. The patch was also tested on a beaglebone black board. The addresses generated for the registers of the loaded drivers are those specified by the AM335x reference manual. Signed-off-by: Dario Binacchi <dariobin@libero.it> Tested-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clk: move clk-ti-sci driver to 'ti' directoryDario Binacchi2021-01-125-9/+9
| | | | | | | | | | | | | | The patch moves the clk-ti-sci.c file to the 'ti' directory along with all the other TI's drivers, and renames it clk-sci.c. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: omap4: add clock manager driverDario Binacchi2021-01-122-1/+23
| | | | | | | | | | | | | | | | | | This minimal driver is only used to bind child devices. For DT binding details see Linux doc: - Documentation/devicetree/bindings/arm/omap/prcm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add support for clkctrl clocksDario Binacchi2021-01-123-0/+161
| | | | | | | | | | | | | | | | | | | | | | Until now the clkctrl clocks have been enabled/disabled through platform routines. Thanks to this patch they can be enabled and configured directly by the probed devices that need to use them. For DT binding details see Linux doc: - Documentation/devicetree/bindings/clock/ti-clkctrl.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add gate clock driverDario Binacchi2021-01-123-0/+100
| | | | | | | | | | | | | | | | | | The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add divider clock driverDario Binacchi2021-01-126-25/+439
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: am33xx: add DPLL clock driversDario Binacchi2021-01-124-0/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add mux clock driverDario Binacchi2021-01-125-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: add clk_round_rate()Dario Binacchi2021-01-123-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | bus: ti: add minimal sysc interconnect target driverDario Binacchi2021-01-123-0/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: export generic routinesDario Binacchi2021-01-121-12/+12
| | | | | | | | | | | | | | | | Export routines that can be used by other drivers avoiding duplicating code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | spi: omap3_spi: Fix speed and mode selectionVignesh Raghavendra2021-01-121-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdataOvidiu Panait2021-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
* | gpio: tca642x: fix input subcommand for gpio banks > 0Tomas Novotny2021-01-121-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of input pin for bank > 0 is always 0 for input subcommand. The reason is that gpio_bank variable is computed only for invert and output subcommands (it depends on number of arguments). The default value of zero causes to shift the mask away for banks > 0. Please note that info subcommand works as expected, because the input pin values are accessed differently. Fixes: 61c1775f16ed ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tomas Novotny <tomas@novotny.cz>
* | Merge tag 'xilinx-for-v2021.04' of ↵Tom Rini2021-01-069-30/+391
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
| * | video: Call video_sync in video_clear()Michal Simek2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is a need to call sync when anybody asking for clearing display. For example via cls command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | video: seps525: Add seps525 SPI driverMichal Simek2021-01-053-0/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB 160x128 display. This driver has been tested through zynq-spi driver. ZynqMP> load mmc 1 100000 rainbow.bmp 61562 bytes read in 20 ms (2.9 MiB/s) ZynqMP> bmp info 100000 Image size : 160 x 128 Bits per pixel: 24 Compression : 0 ZynqMP> bmp display 100000 ZynqMP> setenv stdout vidconsole Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | video: Introduce video_sync operationMichal Simek2021-01-051-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers like LCD connected via SPI requires explicit sync function which copy framebuffer content over SPI to controller to display. This hook doesn't exist yet that's why introduce it via video operations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | video: Let video_sync to return error valueMichal Simek2021-01-053-18/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is preparation for follow up one to support cases where synchronization can fail. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | zynq: mtd: nand: remove superfluous ifHeinrich Schuchardt2021-01-051-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sort of code does not make much sense: if (ondie_ecc_enabled) { if (ondie_ecc_enabled) { Remove the inner if. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | spi: zynqmp_gqspi: Fix unaligned data writes issueT Karthik Reddy2021-01-041-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When unaligned 3 bytes data write operation is performed, 3rd byte is being over written by 1st byte of 3 bytes data. This patch fixes it. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | serial: uartlite: Fix uninitialized ret in debug uartliteAshok Reddy Soma2021-01-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Endianness detection is checked against uninitialized ret variable. Assign ret with read value from status register to fix this. Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-05216-677/+1065
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * | | dtoc: Drop dm_populate_phandle_data()Simon Glass2021-01-051-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has not been needed since parent information was added and we started using indicies for references to other drivers instead of pointers. It was kept around in the expectation that it might be needed later. However with the latest updates, it doesn't seem likely that we'll need this in the foreseeable future. Drop dm_populate_phandle_data() from dtoc and driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIASSimon Glass2021-01-0515-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-0527-39/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Rename U_BOOT_DEVICE() to U_BOOT_DRVINFO()Simon Glass2021-01-0513-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add logging when lists_bind_fdt() failsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to see the error code when this fails. Add logging for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Allow the uclass list to moveSimon Glass2021-01-053-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the uclass list head is in global_data. This is convenient but with the new of-platdata we need the list head to be declared by the generated code. Change this over to be a pointer. Provide a 'static' version in global_data to retain the current behaviour. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Split out scanning code to dm_scan()Simon Glass2021-01-051-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code related to scanning for devices to bind, into a new function. This will make it easier to skip this step with the new of-platdata improvements. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-27 08:43:59 +0000