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| * | | dm: syscon: Fix calling dev_dbg with an uninitialized deviceSean Anderson2020-09-301-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | We can't use dev_dbg here because we haven't bound to the device yet. Use log_debug instead. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 ↵Tom Rini2020-09-257-1/+326
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next - Enhance the 'zboot' command to be more like 'bootm' with sub-commands - The last series of ACPI core changes for programmatic generation of ACPI tables - Add all required ACPI tables for ApolloLake and enable ACPIGEN on Chromebook Coral - A feature minor enhancements to the 'hob' command - Intel edison: Support for writing an xFSTK image via binman
| | * | tpm: cr50: Add ACPI supportSimon Glass2020-09-251-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate ACPI information for this device so that Linux can use it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add common Intel ACPI tablesSimon Glass2020-09-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | i2c: Add a generic driver to generate ACPI infoSimon Glass2020-09-254-0/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many I2C devices produce roughly the same ACPI data with just things like the GPIO/interrupt information being different. This can be handled by a generic driver along with some information in the device tree. Add a generic i2c driver for this purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| | * | dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()Simon Glass2020-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This function currently accepts the IRQ-polarity type. Fix it to use the GPIO type instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini2020-09-2417-56/+106
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
| | * | clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flagMichal Simek2020-09-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fixed-rate driver is not different from clk_fixed_factor and it is required very early in boot that's why setup flag for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | mmc: zynq: Fix incorrect indentationMichal Simek2020-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Trivial fix. Fixes: d1f4e39d58db ("mmc: zynq_sdhci: Add support for SD3.0" Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | fpga: zynqmp: Protect zynqmp_loads() for SPLMichal Simek2020-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | if conditions should match. Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGAMichal Simek2020-09-231-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile and zynqmp.c to simplify if/endif logic in zynqmp.c. This change is mostly done to be able to use CONFIG_IS_ENABLED macro and obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync. And removing one line from Topic Miami boards which is not needed because symbol is not enabled via Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macrosMichal Simek2020-09-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to use these macros because enum pm_api_id can be used instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | net: xilinx: axi_emac: Typecast flush_cache argumentsAshok Reddy Soma2020-09-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flush_cache() arguments are not type casted to take care of 64 bit systems. Use phys_addr_t to type cast for it to work properly for 32 bit and 64 bit systems. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| | * | net: xilinx: axi_emac: Fix dma descriptors for 64bit and compilation warningsAshok Reddy Soma2020-09-231-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are compilation warnings showing up when we compile AXI ethernet driver for 64bit architectures. Fix them, so that it works on both 32 and 64 bit architectures. DMA descriptors are not taking care of 64bit addresses. To fix it, change axidma_bd members as below: next ==> next_desc reserverd1 ==> next_desc_msb phys ==> buf_addr reserverd2 ==> buf_addr_msb and update next_desc and buf_addr with lower 32 bits of the addresses, update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit addresses. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| | * | nand: Kconfig: Change dependency for NAND_ARASANMichal Simek2020-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with !DM that's why Kconfig it showing it as error: WARNING: unmet direct dependencies detected for DM_MTD Depends on [n]: DM [=n] Selected by [y]: - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| | * | serial: uartlite: Add support to work with any endiannessT Karthik Reddy2020-09-231-16/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This endinness changes are taken from linux uartlite driver. Reset TX fifo in control register and check TX fifo empty flag in lower byte of the status register to detect if it is a little endian system. Based on this check, program the registers with le32 or be32 through out the driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek2020-09-233-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. This is follow up patch based on commit 664e16ce99a0 ("xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | net: gem: Add support for more PHYs on MDIO busMichal Simek2020-09-231-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Find out MDIO bus and enable MDIO access to it if this is done via different GEM controller. Only works across GEM instances. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | xilinx: drivers: Use '_' instead of '-' in driver nameMichal Simek2020-09-236-6/+6
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | The most of drivers are using '_' instead of '-' in driver name. That's why sync up these names to be aligned. It looks quite bad to see both in use. It is visible via dm tree command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | net: tsec: Add the compatible string "gianfar" supportHou Zhiqiang2020-09-241-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible string "gianfar" support and update the device-tree-bindings doc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: tsec: Add fixed-link PHY supportHou Zhiqiang2020-09-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The info of fixed-link PHY is described in DT node instead of getting from MII, so detect the fixed-link PHY DT node first, if it doesn't exist then probe the MII. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: tsec: convert to use DM_MDIO when DM_ETH enabledHou Zhiqiang2020-09-241-33/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO. Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Reworked to fix gazerbeam config] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: fsl_mdio: Correct the MII management register block addressHou Zhiqiang2020-09-241-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MII management register block offset is different between gianfar and etsec2 compatible devices, this patch is to fix this issue by adding driver data for different compatible string. Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: fsl_mdio: Change to use virtual addressHou Zhiqiang2020-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use virtual address to access the MII block registers instead of physical address. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | phy: make phy_connect_fixed work with a null mdio busVladimir Oltean2020-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is utterly pointless to require an MDIO bus pointer for a fixed PHY device. The fixed.c implementation does not require it, only phy_device_create. Fix that. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | dm: add cells_count parameter in live DT APIs of_parse_phandle_with_argsPatrick Delaunay2020-09-222-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the live tree API ofnode_parse_phandle_with_args, the cell_count argument must be used when cells_name is NULL. But this argument is not provided to the live DT function of_parse_phandle_with_args even it is provided to fdtdec_parse_phandle_with_args. This patch adds support of the cells_count parameter in dev_ and of_node API to allow migration and support of live DT: - of_parse_phandle_with_args Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: syscon: typo aleradyHeinrich Schuchardt2020-09-221-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Fix typo: %s/alerady/already/. * Add missing 'the'. * Reformat a comment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | Merge branch '2020-09-14-generic-phy-error-trace' into nextTom Rini2020-09-215-19/+54
| |\ \ | | | | | | | | | | | | - Add error tracing messages to the generic PHY infrastructure
| | * | usb: musb-new: sunxi: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the dev_err/pr_err can be change to dev_dbg/pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | ata: dwc-ahci: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the pr_err can be change to pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | usb: host: ehci-hcd: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the pr_err can be change to pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | usb: host: ohci: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the dev_err can be change to dev_dbg. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | phy: generic: add error trace to detect PHY issue in uclassPatrick Delaunay2020-09-081-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an error trace for PHY errors directly in generic phy functions provided by PHY uclass. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | Merge branch 'master' into nextTom Rini2020-09-216-28/+31
| |\ \ \ | | | |/ | | |/| | | | | Merge in v2020.10-rc5
| * | | usb: dwc3: Add Qualcomm DWC3 compatible stringRobert Marko2020-09-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0 ports. Qualcomm has some custom config registers on top of the generic ones, but for host mode these are not needed. So lets add the neccessary compatible string. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko2020-09-183-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | reset: Add IPQ40xx reset controller driverRobert Marko2020-09-183-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | IPQ40xx: Add SMEM supportRobert Marko2020-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is already existing driver for SMEM so lets enable it for IPQ40xx as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | net, qe: add DM support for QE UEC ethernetHeiko Schocher2020-09-1714-1/+2696
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add DM/DTS support for the UEC ethernet on QUICC Engine Block. Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com> Series-changes: 3 - revert: commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled") as now qe works with DM and DM_ETH support. - fix mailaddress from Holger Series-changes: 2 - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag Commit-notes: - I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS. - add the DM based qe uec driver under drivers/net/qe - Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes. - The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c - seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c END
| * | | powerpc, qe: add DTS support for parallel I/O portsHeiko Schocher2020-09-173-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
| * | | powerpc, qe: fix codingstyle issues for drivers/qeHeiko Schocher2020-09-177-972/+1040
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix Codingstyle for files in drivers/qe, remaining following check warnings: $ ./scripts/checkpatch.pl -f drivers/qe/uec.h CHECK: Macro argument reuse '_bd' - possible side-effects? +#define BD_ADVANCE(_bd, _status, _base) \ + (((_status) & BD_WRAP) ? (_bd) = \ + ((struct buffer_descriptor *)(_base)) : ++(_bd)) total: 0 errors, 0 warnings, 1 checks, 692 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h total: 0 errors, 0 warnings, 0 checks, 214 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uccf.c total: 0 errors, 0 warnings, 0 checks, 507 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec.c total: 0 errors, 0 warnings, 0 checks, 1434 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c total: 0 errors, 0 warnings, 0 checks, 927 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/qe.c CHECK: Lines should not end with a '(' +U_BOOT_CMD( total: 0 errors, 0 warnings, 1 checks, 830 lines checked Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | Merge tag 'ti-v2021.01-next' of ↵Tom Rini2020-09-153-91/+117
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next - Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
| | * | | spi: omap3_spi: Read platform data in ofdata_to_platdata()Faiz Abbas2020-09-151-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an ofdata_to_platdata() callback to access dts in U-boot and access all platform data in it. This prepares the driver for supporting both device tree as well as static platform data structures in SPL. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| | * | | arm: mach-omap2: am33xx: Add device structure for spiFaiz Abbas2020-09-151-69/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| | * | | spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failuresFaiz Abbas2020-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are devices which don't use OF_CONTROL or OF_PLATDATA but instead rely on statically defined platdata. Block dm_scan_fdt_dev() with both configs to avoid build failures under this condition. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * | | remoteproc: k3-r5: Add support for J7200 R5FsSuman Anna2020-09-151-10/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: Suman Anna <s-anna@ti.com>
| * | | | PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu2020-09-101-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
| * | | | clock:aspeed: Sync with Linux kernel clock header defineRyan Chen2020-09-091-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
| * | | | cosmetic: aspeed: ast2500: Rename clock headerRyan Chen2020-09-091-1/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| * | | Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of ↵Tom Rini2020-09-072-8/+3
| |\ \ \ | | |/ / | |/| | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
generated by cgit (git 2.34.1) at 2025-09-29 16:22:00 +0000