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* | | clk: sifive: Include device_compat.hSean Anderson2020-10-151-7/+7
|/ / | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | Merge tag 'mmc-2020-10-14' of ↵Tom Rini2020-10-159-229/+482
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * | mmc: fsl_esdhc: add ADMA2 supportMichael Walle2020-10-142-5/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle2020-10-141-73/+65
| | | | | | | | | | | | | | | | | | | | | Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32Haibo Chen2020-10-121-32/+32
| | | | | | | | | | | | | | | | | | | | | Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | mmc: do not check argument of free() beforehandHeinrich Schuchardt2020-10-121-2/+1
| | | | | | | | | | | | | | | | | | free() checks if its argument in NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | mmc: sdhci: move the ADMA2 table handling into own moduleMichael Walle2020-10-124-55/+87
| | | | | | | | | | | | | | | | | | | | | | | | There are other (non-SDHCI) controllers which supports ADMA2 descriptor tables, namely the Freescale eSDHC. Instead of copying the code, move it into an own module. Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc: simplify esdhc_setup_data()Michael Walle2020-10-121-27/+42
| | | | | | | | | | | | | | | | | | | | | | | | First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc: use dma-mapping APIMichael Walle2020-10-121-35/+14
| | | | | | | | | | | | | | | | | | | | | Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc: simplify 64bit check for SDMA transfersMichael Walle2020-10-121-23/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc>
| * | mmc: fsl_esdhc_imx: remove the 1ms delay before sending commandHaibo Chen2020-10-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switchHaibo Chen2020-10-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | According to the code logic in __mmc_switch, if the parameter 'send_status' is zero, no need to send cmd13, just wait the stated timeout time, then can return directly. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * | mmc: fsl_esdhc: fix eMMC HS400 stability issueYangbo Lu2020-10-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a fix-up for eMMC HS400 stability issue in Linux. Patch link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53 Description: Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Introduce the fix-up in u-boot since the issue could be reproduced in u-boot too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: fsl_esdhc: fix mmc->clock with actual clockYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock which was removed accidentally. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu2020-10-121-34/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: add a mmc_hs400_prepare_ddr() interfaceYangbo Lu2020-10-122-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add a mmc_hs400_prepare_ddr() interface for controllers which needs preparation before switching to DDR mode for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: add a hs400_tuning flagYangbo Lu2020-10-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some controllers may have difference between HS200 tuning and HS400 tuning, such as different registers setting, different procedure, or different errata. This patch is to add a hs400_tuning flag to identify the tuning for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during initYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | | | | | | | | Clean TBCTL[TB_EN] manually during init since it is not able to be reset by reset all operation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: fsl_esdhc: support tuning for eMMC HS200Yangbo Lu2020-10-121-3/+103
| | | | | | | | | | | | | | | | | | Support tuning process for eMMC HS200 for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * | mmc: fsl_esdhc: add a reinit() callbackYangbo Lu2020-10-121-0/+9
| | | | | | | | | | | | | | | | | | | | | Add a reinit() callback for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: add a reinit() APIYangbo Lu2020-10-122-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | For DM_MMC, the controller re-initialization is needed to clear old configuration for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-1435-6/+14182
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
| * | | spi: mvebu_a3700_spi: add support for cs-gpiosGeorge Hilliard2020-10-141-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree has a way to specify GPIO lines as chip selects. From the binding docs: So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : &gpio1 0 0 cs1 : native cs2 : &gpio1 1 0 cs3 : &gpio1 2 0 Add support for this, while retaining backward-compatibility with existing device trees; the driver will preserve existing behavior if a cs-gpios list is not given, or if a particular line is specified as <0> (native). This implementation is inspired by similar implementations in neighboring drivers for other platforms: atmega, mxc, etc. Signed-off-by: George Hilliard <ghilliar@amazon.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | net: Add NIC controller driver for OcteonTX2Suneel Garapati2020-10-1416-0/+4493
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | | net: Add NIC controller driver for OcteonTXSuneel Garapati2020-10-1414-0/+6656
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | | mtd: nand: Add NAND controller driver for OcteonTXSuneel Garapati2020-10-146-0/+2998
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | net: e1000: add defaults for i210 TX/RX PBSIZEChristian Gmeiner2020-10-142-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the defaults on probe for the packet buffer size registers for the i210. The TX/RX PBSIZE register of the i210 resets to its default value only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5 chapter 8.3 'Internal Packet Buffer Size Registers'. If something (another driver, another OS, etc.) modifies this register from its default value, the e1000 driver doesn't function correctly. It detects a hang of the transmitter and continuously resets the adapter. Here we set this value to its default when resetting the i210 to resolve this issue. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* | | | treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak2020-10-143-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | mmc: remove duplicate mmc_get_env_dev() implementationsDavid Woodhouse2020-10-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since it's so trivial I could just about tolerate this when there were only two copies of it. But now there are about to be three. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* | | | drivers: gpio: keep output value for input on sandboxHeinrich Schuchardt2020-10-141-1/+9
|/ / / | | | | | | | | | | | | | | | | | | | | | For testing purposes keep the output value when switching to input. This allows us to manipulate the input value via the gpio command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* | | Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini2020-10-128-33/+118
|\ \ \
| * | | arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang2020-10-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-094-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang2020-10-093-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | clk: agilex: Additional membus writes for HPS PLLChee Hong Ang2020-10-091-16/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang2020-10-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | | clk: agilex: Add clock enable supportLey Foon Tan2020-10-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | | clk: agilex: Add NAND clock supportLey Foon Tan2020-10-091-0/+3
| | |/ | |/| | | | | | | | | | | | | | | | Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | | Merge tag 'ti-v2021.01-rc1' of ↵Tom Rini2020-10-122-4/+11
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Minor cleanup on K3 env variables - Fix OSPI compatible for J721e - Drop unused property in omap-usb2-phy - Update Maintainer for am335x-guardian board.
| * | phy: omap-usb2-phy: Drop usage of "ti, dis-chg-det-quirk" DT propertyVignesh Raghavendra2020-10-121-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | "ti,dis-chg-det-quirk" property is not part of Linux kernel DT binding documentation. Therefore drop this and instead use soc_device_match() to distinguish b/w AM654 SR1.0 and SR2.0 devices similar to Linux kernel driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | dma: ti: k3-udma: Reset the channel during releaseVignesh Raghavendra2020-10-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Reset the channel completely during channel release in order to clear teardown bit before handing over to next user or jumping to Linux. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | | Kconfig: Move BOUNCE_BUFFER under driver optionsSimon Glass2020-10-091-0/+11
| | | | | | | | | | | | | | | | | | | | | This option does not belong at the top level. Move it under generic driver options. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | wdt: designware: fix timeout calculation due to expecting KHzJack Mitchell2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The timeout calculation is based on the clk being in KHz but the clk api returns the clk value in Hz. Convert this to KHz to calculate the correct timeout value. Signed-off-by: Jack Mitchell <ml@embed.me.uk>
* | | led: gpio: Default to using node name if label is absentSean Anderson2020-10-081-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | This more closely mirrors Linux's behaviour, and will make it easier to transition to using function+color in the future. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | gpio: dw: Return output value when direction is outSean Anderson2020-10-081-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | dm_gpio_ops.get_value can be called when the gpio is either input or output. The current dw code always returns the input value, which is invalid if the direction is set to out. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | | gpio: dw: Add a trailing underscore to generated nameSean Anderson2020-10-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, if there was no bank-name property, it was easy to have confusing gpio names like "gpio1@08", instead of "gpio1@0_8". This patch follows the example of the sifive gpio driver. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | gpio: dw: Fix warnings about casting int to pointerSean Anderson2020-10-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the type of gpio_dwabp_platdata.base from fdt_addr_t to a void pointer, since we pass it to readl. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | pinctrl: Add support for Kendryte K210 FPIOASean Anderson2020-10-083-0/+745
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-28 19:32:21 +0000