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* | | i2c: designware: Use log_debug() for debuggingSimon Glass2020-10-221-2/+2
| | | | | | | | | | | | | | | | | | | | | We don't want the debug output to be visible in a normal boot. Silence it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de>
* | | syscon: Drop the logging in syscon_get_by_driver_data()Simon Glass2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be called when it is not known whether it will find anything. This results in confusing log messages if the device is not found. It is better for the caller to log the failure, if necessary. Drop the logging from this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini2020-10-223-17/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
| * | | arm: stm32: cleanup arch gpio.hPatrick Delaunay2020-10-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc2020-10-211-16/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc2020-10-211-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2020-10-208-28/+1059
|\ \ \ | | | | | | | | | | | | - Assorted R-Car Gen3 updates
| * | | pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9Lad Prabhakar2020-10-201-27/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar2020-10-203-0/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | clk: renesas: Add R8A774E1 clock tablesBiju Das2020-10-203-0/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | clk: renesas: Add R8A774B1 clock tablesBiju Das2020-10-203-0/+343
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das2020-10-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility stringBiju Das2020-10-201-1/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | | usb: gadget: Add bcdDevice for the MTU3 USB Gadget ControllerChunfeng Yun2020-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add an entry in usb_gadget_controller_number() for the MTU3 gadget controller. It is used to bind the USB Ethernet driver. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: add MediaTek USB3 DRD driverChunfeng Yun2020-10-2013-0/+4557
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: common: add define of usb_speed_string()Chunfeng Yun2020-10-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | There is only declaration of usb_speed_string(), but no definition, so add it to avoid build error when call it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: add USB_SPEED_SUPER_PLUSChunfeng Yun2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | Add enum USB_SPEED_SUPER_PLUS for USB3.1 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: musb-new: Fix typo in caution messageNaoki Hayama2020-10-201-1/+1
| | | | | | | | | | | | | | | | | | %s/Occured/Occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
* | | usb: dwc2: Fix control OUT transfer issueChance.Yang2020-10-201-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In buffer DMA mode, gadget should re-configure EP 0 to received SETUP packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes) and EP 0 is in WAIT_FOR_SETUP state. Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT received from RxFifo and wriiten to the external memory. Signed-off-by: Chance.Yang <chance.yang@vatics.com>
* | | usb: xhci: avoid type conversion of void *Heinrich Schuchardt2020-10-201-12/+9
|/ / | | | | | | | | | | | | void * can be assigned to any pointer variable. Avoid unnecessary conversions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini2020-10-195-4/+654
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
| * | clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev2020-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2020-10-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea2020-10-192-0/+650
| | | | | | | | | | | | | | | | | | Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | | configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay2020-10-181-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay2020-10-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay2020-10-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | video: backlight: fix pwm's duty cycle calculationDario Binacchi2020-10-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | video: backlight: fix pwm data structure descriptionDario Binacchi2020-10-181-1/+1
| | | | | | | | | | | | | | | | | | | | | The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | | video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong2020-10-181-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong2020-10-181-6/+11
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-163-7/+87
|\ \ | | | | | | | | | | | | | | | - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
| * | watchdog: octeontx_wdt: Add support for start and stopSuneel Garapati2020-10-161-5/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the Octeon TX/TX2 watchdog driver to fully enable the WDT. With this changes, the "wdt" command is now also supported on these platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * | mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese2020-10-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * | spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese2020-10-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
* | | usb: dwc3: Include device_compat.h in dwc3-octeon-glue.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | clk: at91: Include device_compat.h in compat.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | usb: musb-new: mt85xx: Fix not calling dev_err with a deviceSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | | | | | | | | | | This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | usb: musb-new: Include device_compat.hSean Anderson2020-10-165-1/+11
| | | | | | | | | | | | | | | | | | | | | This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | usb: xhci: Include device_compat.hSean Anderson2020-10-162-5/+7
| | | | | | | | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | timer: Include device_compat.hSean Anderson2020-10-161-2/+3
| | | | | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | tee: optee: Include device_compat.hSean Anderson2020-10-161-0/+1
| | | | | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | spi: fsl_qspi: Include device_compat.hSean Anderson2020-10-161-4/+5
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | spi: nxp_fspi: Include device_compat.hSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | ram: imxrt: Include device_compat.hSean Anderson2020-10-151-0/+1
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | phy: Include device_compat.hSean Anderson2020-10-151-1/+1
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | net: ldpaa_eth: Include device_compat.hSean Anderson2020-10-151-7/+7
| | | | | | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson2020-10-151-13/+15
| | | | | | | | | | | | | | | | | | This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | firmware: scmi: Include device_compat.hSean Anderson2020-10-153-0/+3
| | | | | | | | | | | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | dm: syscon: Set LOG_CATEGORYSean Anderson2020-10-151-0/+2
| | | | | | | | | | | | | | | | | | | | | We call log_debug, but do not have a category set. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-28 17:53:13 +0000