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| * | | pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2020-10-232-0/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: move pci node search in a common functionLaurentiu Tudor2020-10-231-42/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: move per-pci device fdt fixup in a functionLaurentiu Tudor2020-10-231-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pci device related fdt fixup in a function in order to re-use it in a following patch. While at it, improve the error handling. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | | drivers: mux: mmio-based syscon mux controllerJean-Jacques Hiblot2020-10-283-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for mmio-based syscon multiplexers controlled by bitfields in a syscon register range. This is heavily based on the linux mmio-mux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* | | | dm: board: complete the initialization of the muxes in initr_dm()Jean-Jacques Hiblot2020-10-281-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will probe the multiplexer devices that have a "u-boot,mux-autoprobe" property. As a consequence they will be put in their idle state. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* | | | drivers: Add a new framework for multiplexer devicesJean-Jacques Hiblot2020-10-285-0/+332
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | rtc: provide an emulated RTCHeinrich Schuchardt2020-10-273-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a board without hardware clock this software real time clock can be used. The build time is used to initialize the RTC. So you will have to adjust the time either manually using the 'date' command or use the 'sntp' to update the RTC with the time from a network time server. See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU ticks. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | | Merge tag 'video-for-2021.01-rc1' of ↵Tom Rini2020-10-261-1/+8
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-video - disable CONFIG_VIDEO to remove DM conversion warnings for boards: at91sam9, eb_cpu5282, ls1021aqds, ls1021atwr, mx23evk, mx6sxsabresd, mx7dsabresd, nokia_rx51, picosam9g45, sansa_fuze_plus, xfi3
| * | | | nokia_rx51: disable obsolete VIDEO configAnatolij Gustschin2020-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable VIDEO config to fix DM_VIDEO conversion deadline warning. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | | eb_cpu5282: fix CONFIG_DM_VIDEO build warningsAnatolij Gustschin2020-10-261-0/+7
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_VIDEO dependency to fix board removal warnings. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Jens Scharsig <esw@bus-elektronik.de>
* | | | riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson2020-10-262-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: Move Andes PLMT driver to drivers/timerSean Anderson2020-10-263-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | clk: kendryte: no need to check argument of free()Heinrich Schuchardt2020-10-261-2/+1
|/ / / | | | | | | | | | | | | | | | | | | free() checks if its argument is NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | | phy: nop-phy: add clk bulkPeng Fan2020-10-231-0/+35
| | | | | | | | | | | | | | | | | | Add clk bulk for nop-phy driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | i2c: i2c-gpio: Convert to use APIs which support live DTPatrick Delaunay2020-10-231-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | power: regulator: gpio-regulator: Convert to use APIs which support live DTPatrick Delaunay2020-10-231-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | power: regulator: gpio-regulator: protect count valuePatrick Delaunay2020-10-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the size of states_array to avoid overflow for dev_pdata->voltages[j] and dev_pdata->states[j]. As the size of array is GPIO_REGULATOR_MAX_STATES, the size of states_array is limited by GPIO_REGULATOR_MAX_STATES * 2 = 4 instead of 8 previously. The value of the "count" variable is limited by the third parameter of fdtdec_get_int_array_count. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Revert "serial: serial_xen: print U-Boot banner and others"Tom Rini2020-10-231-0/+2
| | | | | | | | | | | | | | | | | | This reverts commit 18426bf02217de2e9bb2b41eaa74d769892c55ef. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Revert "serial: serial_xen: add DEBUG_UART support"Tom Rini2020-10-232-31/+3
| | | | | | | | | | | | | | | | | | This reverts commit 82e21b391bd315f6fe0e0b79326af8a141e9cca7. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2020-10-221-251/+206
|\ \ \ | |/ / |/| | | | | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * | net: sun8i-emac: Lower MDIO frequencyAndre Przywara2020-10-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i-emac: Make internal PHY handling more robustAndre Przywara2020-10-211-32/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Simplify and fix error handling for RXAndre Przywara2020-10-211-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix MAC soft resetAndre Przywara2020-10-211-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix overlong linesAndre Przywara2020-10-211-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Wrap and simplify cache maintenance operationsAndre Przywara2020-10-211-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Drop unneeded cache invalidation before sendingAndre Przywara2020-10-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Reduce cache maintenance on TX descriptor initAndre Przywara2020-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Improve cache maintenance on RX descriptor initAndre Przywara2020-10-211-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Name magic bits and simplify read-modify-write callsAndre Przywara2020-10-211-52/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Remove pointless wrapper functionsAndre Przywara2020-10-211-46/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Simplify mdio_read/mdio_write functionsAndre Przywara2020-10-211-41/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Don't hand out TX descriptor too earlyAndre Przywara2020-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i-emac: Bail out on PHY errorAndre Przywara2020-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | rtc: move pcf8563 to KconfigHeiko Schocher2020-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | add Kconfig option for pcf8563 driver and run tools/moveconfig.py Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* | | mmc: mtk-sd: change some dev_err into dev_dbgFabien Parent2020-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | dev_err has been used for debugging and a few dev_err message are printed for normal code execution. Make them dev_dbg instead. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | serial: serial_xen: add DEBUG_UART supportAKASHI Takahiro2020-10-222-3/+31
| | | | | | | | | | | | | | | | | | | | | By using a hypervisor call, we can implement DEBUG_UART on xen. This will allow us to see messages even earlier than serial_init(). Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
* | | serial: serial_xen: print U-Boot banner and othersAKASHI Takahiro2020-10-221-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, DM_FLAG_PRE_RELOC is set only if !OF_CONTROL. It doesn't make sense for this para-virtualized driver. With this patch applied, you will be able to see early boot messages: U-Boot 2020.10-00001-ge442e71a6c52-dirty (Oct 15 2020 - 11:02:25 +0900) xenguest Xen virtual CPU Model: XENVM-4.15 DRAM: 128 MiB PVBLOCK: (XEN) gnttab_mark_dirty not implemented yet pvblock: 0 In: hypervisor Out: hypervisor Err: hypervisor xenguest# Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | cosmetic: reset: ast2500: Rename driver and configsChia-Wei, Wang2020-10-223-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Rename AST2500 reset driver from ast2500-reset.c to reset-ast2500.c 2. Rename AST2500 reset kconfig option from AST2500_RESET to RESET_AST2500 Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-222-51/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | clk: ccf: replace the get_rate helperDario Binacchi2020-10-221-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The 12d152620d commit fixed the get_rate helper because the set_parent one did not re-parent the clock device to the new parent. The 4d139f3838 commit allows you to remove this workaround by calling the clk_get_parent_rate routine. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | | ARM: mvebu: a38x: Fix comment typoNaoki Hayama2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | %s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp> Reviewed-by: Stefan Roese <sr@denx.de>
* | | mmc: Fix comment typoNaoki Hayama2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | %s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
* | | rng: Add Qualcomm MSM PRNG driverRobert Marko2020-10-223-0/+151
| | | | | | | | | | | | | | | | | | | | | Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | net: Add IPQ40xx MDIO driverRobert Marko2020-10-223-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | spi: Add Qualcomm QUP SPI controller driverRobert Marko2020-10-223-0/+814
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | timer: Return count from timer_ops.get_countSean Anderson2020-10-2221-86/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | No timer drivers return an error from get_count. Instead of possibly returning an error, just return the count directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | common: rename getc() to getchar()Heinrich Schuchardt2020-10-224-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandbox is built with the SDL2 library with invokes the X11 library which in turn calls getc(). But getc() in glibc is defined as int getc(FILE *) This does not match our definition. int getc(void) The sandbox crashes when called with parameter -l. Rename our library symbol getc() to getchar(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | tpm: cr50: Correct logging statementsSimon Glass2020-10-221-5/+5
| | | | | | | | | | | | | | | | | | | | | Fix up some logging statements in this file. Most of them should use log_debug(), apart from one error. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-28 12:50:42 +0000