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* | Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini2020-10-305-2/+57
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
| * | video: rockchip: Support 4K resolution for rk3288, HDMIJagan Teki2020-10-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like, rk3399 the rk3288 also supports 4K resolution. So, enable it for rk3288 with HDMI platforms. Right now, rockchip video drivers are supporting for rk3288, rk3399 SoC families, so mark the 4K resolution by default if it's an HDMI video out. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | video: rockchip: Add missing dpcd_write() call to link_train_ce()Alper Nebi Yasak2020-10-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found this by comparing it to the coreboot driver, a form of this call was introduced there in their commit b9a7877568cf ("rockchip/*: refactor edp driver"). This is copy-pasted from U-Boot's link_train_cr() slightly above it. Without this on a gru-kevin chromebook, I have: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB channel eq failed, ret=-5 link train failed! rk_vop_probe() Device failed: ret=-5 With this, it looks like training succeeds: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 config video failed rk_vop_probe() Device failed: ret=-110 The "config video failed" error also goes away when I disable higher log levels, and it claims to have successfully probed the device. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2020-10-302-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell2020-10-301-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge tag 'dm-pull-30oct20' of ↵Tom Rini2020-10-3021-111/+165
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
| * | | dm: Use driver_info index instead of pointerSimon Glass2020-10-294-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Take advantage of the of-platdata parent supportSimon Glass2020-10-291-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass2020-10-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Convert #ifdef to if() in root.cSimon Glass2020-10-291-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert a few conditions to use compile-time checks to reduce the number of build paths. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Add a test for of-platdata parent informationSimon Glass2020-10-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple test that we can obtain the correct parent for an I2C device. This requires updating the driver names to match the compatible strings, adding them to the devicetree and enabling a few options. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Support parent devices with of-platdataSimon Glass2020-10-291-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present of-platdata does not provide parent information. But this is useful for I2C devices, for example, since it allows them to determine which bus they are on. Add support for setting the parent correctly, by storing the parent driver_info index in dtoc and reading this in lists_bind_drivers(). This needs multiple passes since we must process children after their parents already have been bound. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Fix up building for of-platdataSimon Glass2020-10-293-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no devicetree with of-platdata. Update a few uclasses to allow them to be built for sandbox_spl. Also drop the i2c-gpio from SPL to avoid build errors, since it does not support of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Use an allocated array for run-time device infoSimon Glass2020-10-293-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we update the driver_info struct with a pointer to the device that it created (i.e. caused to be bound). This works fine when U-Boot SPL is stored in read-write memory. But on some platforms, such as Intel Apollo Lake, it is not possible to update the data memory. In any case, it is bad form to put this information in a structure that is in the data region, since it expands the size of the binary. Create a new driver_rt structure which holds runtime information about drivers. Update the code to store the device pointer in this instead. Also update the test check that this works. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Add a test for of-platdata phandlesSimon Glass2020-10-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a test in dtoc for this feature, but not one in U-Boot itself. Add a simple test that checks that the information comes through correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Add a check that all devices have a dev valueSimon Glass2020-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With of-platdata, the driver_info struct is updated with the device pointer when it is bound. This makes it easy for a device to be found by its driver info with the device_get_by_driver_info() function. Add a test that all devices (except the root device) have such an entry. Fix a bug that the function does not set *devp to NULL on failure, which the documentation asserts. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: test: Drop of-platdata pytestSimon Glass2020-10-291-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have a C version of this test, drop the Python implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Allow dm_warn() to be used in SPLSimon Glass2020-10-292-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this option is disabled in SPL, meaning that warnings are not displayed. It is sometimes useful to see warnings in SPL for debugging purposes. Add a new Kconfig option to permit this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Drop ad-hoc device declarations in SPLSimon Glass2020-10-292-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since sandbox's SPL is build with of-platadata, we should not use U_BOOT_DEVICE() declarations as well. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Avoid using #ifdef for CONFIG_OF_LIVESimon Glass2020-10-292-19/+10
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | At present this option results in a number of #ifdefs due to the presence or absence of the global_data of_root member. Add a few macros to global_data.h to work around this. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-293-1248/+205
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
| * | | mtd: nand: pxa3xx: enable NAND controller if the SoC needs itShmuel Hazan2020-10-292-10/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable NAND controller if the SoC needs it"). This commit adds support for the Armada 8040 nand controller. The kernel commit says this: Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | mtd: pxa3xx_nand: remove dead codeBaruch Siach2020-10-291-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kfree() call is unreachable, and is not needed. Remove this call and the fail_disable_clk label. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | mtd: pxa3xx_nand: port to use driver modelShmuel Hazan2020-10-292-63/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic DT code to find the device compatible property for us. This makes the driver look more like other current drivers. It also make it easier to add support for other variants like Armada 8K in a future commit. Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: update mode parameter for pcie power on callsIgal Liberman2020-10-291-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It helps ATF to determine who called power on function (U-boot/Linux). The corresponding ATF code was added in this commit: mvebu: cp110: avoid pcie power on/off sequence when called from Linux https://github.com/ARM-software/arm-trusted-firmware/commit/55df84f974ea37abbb4f93f000f101f70cda5303 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: let the firmware configure comphy for PCIeGrzegorz Jaszczyk2020-10-291-439/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the comphy initialization for PCIe with appropriate SMC call, so the firmware will perform appropriate comphy initialization. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | phy: marvell: cp110: let the firmware configure the comphyGrzegorz Jaszczyk2020-10-291-727/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all comphy initialization with appropriate smc calls. It will result with triggering synchronous exception that is handled by Secure Monitor code in EL3. Then the Secure Monitor code will dispatch each smc call (by parsing the smc function identifier) and triggers appropriate comphy initialization. This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI interfaces. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | | Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-2911-66/+524
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * | | mmc: zynq_sdhci: Extend UHS timings till hs200Ashok Reddy Soma2020-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the condition to set UHS timings for speeds upto HS200. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma2020-10-271-4/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma2020-10-271-5/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define and use functions for setting input and output tapdelays based on clk phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek2020-10-271-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define input and output clock phase delays with pre-defined values. Define arasan_sdhci_clk_data type structure and add it to priv structure and store these clock phase delays in it. Read input and output clock phase delays from dt. If these values are not passed through dt, use pre-defined values. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: zynq_sdhci: Move macro to the topMichal Simek2020-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just group macros below headers. Other patches will be using this location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: Define timing macro'sAshok Reddy Soma2020-10-271-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | | Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma2020-10-272-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | | spi: zynq_qspi: Add function descriptionAshok Reddy Soma2020-10-271-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect. Fix zqspi to priv in function descriptions. Change the description of priv as pointer to zynq_qspi_priv structure. Fix other function descriptions to kernel-doc style. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | mtd: spi: Fix incorrect indentationMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use tabs to be aligned with the rest of the code. Fixes: 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board KconfigMichal Simek2020-10-271-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to have ZYNQ specific Kconfig macro in generic location to be visible for all other SoCs. That's why move it to Xilinx common location to be visible only for us. Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to disable it or enable. This has connection to code which is reading the whole content of i2c and also work with the rest of date not just with MAC address. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | spi: zynq_qspi: Use clk subsystem to get reference qspi clkT Karthik Reddy2020-10-271-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | spi: zynq_spi: Use clk subsystem to get reference spi clkT Karthik Reddy2020-10-271-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | serial: pl01x: Add error value checkingMichal Simek2020-10-271-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There also a need to check return values to make sure that clocks were enabled and setup properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add support for getting node from aliasesMichal Simek2020-10-271-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for getting a node/property from aliases. The similar functionality is provided for chosen node and this implemenatation is copy of it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | spi: xilinx_spi: remove unused local variableT Karthik Reddy2020-10-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused variable 'count' which is causing warning while compilation. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | mailbox: zynqmp: Extend timeout for getting observation bitMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of fpga loading (which can be huge) 100ms is not enough. That's why extend timeout 10 times to wait maximum 1s to get ACK back. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is calledMichal Simek2020-10-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't know reason but in regular flow addr_hi/low are swapped in ATF. It means when fpga load is done from EL3 there is a need to swap it for PMUFW to load bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | spi: xilinx_spi: Remove unused variableMichal Simek2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused variable: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable] 254 | u32 reg, count, timeout; | ^~~~~~~ Fixes: 0c0de58f7b30 ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-296-92/+512
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * | | dm: pci: fsl: Correct the workaround of erratum A-007815Hou Zhiqiang2020-10-232-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | gpio: mpc8xxx: support fsl-layerscape platformhui.song2020-10-231-21/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the MPC8XXX gpio driver to support the fsl-layerscape. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit (git 2.34.1) at 2025-09-28 09:36:21 +0000