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| * | pci: layerscape: fix a dead loop issueHou Zhiqiang2020-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Fixed checkpatch error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal2020-12-106-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to KconfigMeenakshi Aggarwal2020-12-102-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: ls_pcie_g4: Add size check for config resourceWasim Khan2020-12-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Add size check for config resourceWasim Khan2020-12-101-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: ls_pcie_g4: Print pcie controller number starting from 1Wasim Khan2020-12-101-4/+7
| | | | | | | | | | | | | | | | | | Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
| * | pci: layerscape: Update print of pcie controllerWasim Khan2020-12-102-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Trimmed subject] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini2020-12-0914-14/+14
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
| | * | treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2020-12-0914-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | power: pmic: add SPL_DM_PMIC_PCA9450 symbol to KconfigIgor Opaniuk2020-12-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPL_DM_PMIC_PCA9450 symbol to Kconfig. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | pca9450a: fix i2c addressMax Krummenacher2020-12-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C address is 0x25, not 0x35. This according to the datasheet and tests with a PCA9450A. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: fsl_esdhc_imx: optimize the timing settingHaibo Chen2020-12-061-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the card clock will be divied by 2 automatically by the host. So need to first config the DDR_EN correctly, then update the card clock. This will make sure the actual card clock is as our expected. IC also suggest config the DDR_EN firstly, then config the clock divider. For HS400/HS400ES mode, need to config the strobe dll, this need to based on the correct target clock rate, so need to do this after clock rate is update. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: fsl_esdhc_imx: add wait_dat0() supportHaibo Chen2020-12-061-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | imx: clk: added IPG Clock for I2C on imx8qmOliver Graute2020-12-061-0/+24
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes this clk issue on I2C on imx8qm => i2c bus Bus 3: i2c@5a830000 => i2c dev 3 Setting bus to 3 Failed to enable ipg clk Failure changing bus number (-524) Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | mtd: spi-nor-ids: add Winbond W25Q32JW-IM flashMichael Walle2020-12-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kontron SMARC-sAL28 board uses that flash. This is the same change as in the linux commit f3418718c0ec ("mtd: spi-nor: Add support for w25q32jwm"). Signed-off-by: Michael Walle <michael@walle.cc> Reported-by: Leo Krueger <leo.krueger@zal.aero>
| * | watchdog: sbsa: timeout should be in "millisecond"Zhao Qiang2020-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | timeout should be in "millisecond" instead of second, so divided it by 1000 when calculate the load value. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
| * | Merge tag 'dm-pull-30nov20' of git://git.denx.de/u-boot-dmTom Rini2020-12-022-11/+9
| |\ \ | | | | | | | | | | | | Minor bugfixes
| | * | dm: core: Fix incorrect flag checkMarek Vasut2020-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test should be checking whether $flags are non-zero and $drv_flags contain specific flags, however these two sets of flags are separate, and the two tests should be logically ANDed, not bitwise ANDed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: cros_ec: Basic support for EC_CMD_GET_NEXT_EVENTAlper Nebi Yasak2020-11-301-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this command, but the sandbox EC emulator does not recognize it and continuously prints: ** Unknown EC command 0x67 This patch makes the sandbox driver send basic responses to the command, but the response only supports keyboard scans for now. The EC side of this command stores and returns events from a queue, and returns -EC_RES_UNAVAILABLE when there are no new events. This should be possible to implement by hooking into the SDL event queue (perhaps via sandbox_sdl_poll_events). Implementing that is a bit harder to do since the existing sandbox code is discarding pending keyboard events, then reading the current keyboard state. Since the EC emulator never explicitly fails to work on this command, the fallback to the older command will not trigger and will not be tested anymore. Fixes: 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | mips: octeon: Fix Octeon DDR driver to use the correct structStefan Roese2020-11-301-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use "platdata_auto_alloc_size" but "priv_auto_alloc_size" instead to auto allocate the private data struct, which is referenced via dev_get_priv() in this driver. This fixes an ugly bug detected while trying to boot via SPI NOR. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | dfu_mtd: Add provision to unlock mtd deviceSughosh Ganu2020-12-311-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to writing to an mtd device, mtd_erase is called. This call fails in case the sector being erased is locked. Call mtd_unlock to unlock the region which is to be erased and later written to. Lock the region once the write to the region has completed. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
* | | dm: core: Inline a few ofnode functions in SPLSimon Glass2020-12-222-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent change to unify the flattree/livetree code introduced a small size increase in SPL on some boards. For example SPL code size for px30-core-ctouch2-px30 increased by 40 bytes. To address this we can take advantage of the fact that some of the ofnode functions are only called a few times in SPL, so it is worth inlining them. Add new Kconfig options to control this. These functions are not inlined for U-Boot proper, since this increases code size. Fixes: 2ebea5eaebf ("dm: core: Combine the flattree and livetree binding code") Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: spi: Fix spi_free_slave() freed memory writeNiel Fourie2020-12-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove setting slave->dev to NULL after the device_remove() call. The slave pointer points to dev->parent_priv, which has already been freed by device_free(), called from device_remove() in the preceding line. Writing to slave->dev may cause corruption of the dlmalloc free chunk forward pointer of the previously freed chunk. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logicOvidiu Panait2020-12-222-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when different spi slaves claim the bus consecutively using spi_claim_bus(), spi_set_speed_mode() will only be executed on the first two calls, leaving the bus in a bad state starting with the third call. This patch drops spi_slave->speed member and adds caching of bus speed/mode in dm_spi_bus struct. It also updates spi_claim_bus() to call spi_set_speed_mode() if either speed or mode is different from what the bus is currently configured for. Current behavior is to only take into account the speed, but not the mode, which seems wrong. Fixes: 60e2809a848 ("dm: spi: Avoid setting the speed with every transfer") Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reported-by: Moshe, Yaniv <yanivmo@amazon.com> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
* | | test: spi: Add sandbox_spi_get_{speed, mode} interfaceOvidiu Panait2020-12-221-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce sandbox_spi_get_{speed, mode} public interface to retrieve the sandbox spi bus internal state. They are meant to be used in sandbox spi testcases. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | spi: sandbox_spi: Implement speed/mode setupOvidiu Panait2020-12-221-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | Implement sandbox_spi_set_{speed, mode} routines, to be able to keep track of the current bus speed/mode. This will help determine whether the values passed from dm_spi_claim_bus() are valid. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
* | | sandbox: test: Add a second SPI slave on sandbox_spi busOvidiu Panait2020-12-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Place a second spi slave on the sandbox_spi bus, to be used by the spi_claim_bus() testcase we are about to introduce. We need to make sure that jumping between slaves calling spi_claim_bus() sets the bus speed and mode appropriately. Use different max-hz and mode properties for this new slave. Also, update sandbox_spi cs_info call to allow activity on CS0/CS1 and adapt dm_test_spi_find() testcase for this new setup. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sandbox: spi: Drop unused sandbox_spi_parse_spec functionOvidiu Panait2020-12-221-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1289e96797bf ("sandbox: spi: Drop command-line SPI option") dropped support for specifying SPI devices on the command line, removing the only user of sandbox_spi_parse_spec(). Remove the function too. Fixes: 1289e96797bf ("sandbox: spi: Drop command-line SPI option") Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Drop seq and req_seqSimon Glass2020-12-182-16/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that migration to the new sequence numbers is complete, drop the old fields. Add a test that covers the new behaviour. Also drop the check for OF_PRIOR_STAGE since we always assign sequence numbers now. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | cmd: Drop use of old sequence numbers in commandsSimon Glass2020-12-181-2/+2
| | | | | | | | | | | | | | | | | | Several commands use sequence numbers. Update them to use the new ones. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Update uclass_find_next_free_req_seq() for new schemeSimon Glass2020-12-183-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | This function current deals with req_seq which is deprecated. Update it to use the new sequence numbers, putting them above existing aliases. Rename the function to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Drop the unused arg in uclass_find_device_by_seq()Simon Glass2020-12-184-30/+16
| | | | | | | | | | | | | | | | | | | | | | | | Now that there is only one sequence number (rather than both requested and assigned ones) we can simplify this function. Also update its caller to simplify the logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Drop uclass_resolve_seq()Simon Glass2020-12-182-47/+0
| | | | | | | | | | | | | | | | | | This function is not needed anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Switch over to use new sequence number for dev_seq()Simon Glass2020-12-181-4/+2
| | | | | | | | | | | | | | | | | | | | | Update this function to use the new sequence number and fix up the test that deals with this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | pinctrl: Update for new sequence numbersSimon Glass2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | Use the dev_seq() sequence number in all cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | gpio: Update for new sequence numbersSimon Glass2020-12-185-5/+5
| | | | | | | | | | | | | | | | | | Use the dev_seq() sequence number in all cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | usb: Update for new sequence numbersSimon Glass2020-12-181-4/+2
| | | | | | | | | | | | | | | | | | | | | Use the new sequence number in all cases. Since all devices are assigned a number when bound, this hack should not be needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | usb: ehci-mx6: Drop assignment of sequence numberSimon Glass2020-12-181-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | This hack cannot work in the new sequence-numbering scheme. Remove it while we wait for the maintainer to complete DM conversion as noted in the existing comment. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | spi: Update for new sequence numbersSimon Glass2020-12-182-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the new sequence number in all cases. Drop the rockchip case because the sequence number should be 0 anyway, and assigning to the sequence number is not permitted. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | pci: Update to use new sequence numbersSimon Glass2020-12-182-23/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Allow manual sequence numberingSimon Glass2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some buses have their own rules which require assigning sequence numbers with a bus-specific algorithm. For example, PCI requires that sub-buses are numbered higher than their parent buses, meaning effectively that parent buses must be numbered only after all of their child buses have been numbered. Add a uclass flag to indicate that driver model should not assign sequence numbers. In this case, the uclass must do it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | net: Update to use new sequence numbersSimon Glass2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking for seq == -1 is effectively checking that the device is activated. The new sequence numbers are never -1 for a bound device, so update the check. Also drop the note about valid sequence numbers so it is accurate with the new approach. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | i2c: Update for new sequence numbersSimon Glass2020-12-186-80/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new sequence number in all cases. Drop the logic to check for a valid number in designware_i2c, since it will always be valid. Also drop the numbering in the uclass, since we can rely on driver model giving us the right sequence numbers. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | octeon: Don't attempt to set the sequence numberSimon Glass2020-12-183-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Several Octeon drivers operate by setting the sequence number of their device. This should not be needed with the new sequence number setup. Also it is not permitted. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Fix return value in dev_read_alias_seq()Simon Glass2020-12-181-1/+3
| | | | | | | | | | | | | | | | | | This should return 0 on success but currently does not. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Switch binding to use new sequence numbersSimon Glass2020-12-181-4/+1
| | | | | | | | | | | | | | | | | | | | | Update the core logic to use the new approach. For now the old code is left as is. Update one test so it still passes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Add a new sequence number for devicesSimon Glass2020-12-182-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present each device has two sequence numbers, with 'req_seq' being set up at bind time and 'seq' at probe time. The idea is that devices can 'request' a sequence number and then the conflicts are resolved when the device is probed. This makes things complicated in a few cases, since we don't really know what the sequence number will end up being. We want to honour the bind-time requests if at all possible, but in fact the only source of these at present is the devicetree aliases. Since we have the devicetree available at bind time, we may as well just use it, in the hope that the required processing will turn out to be useful later (i.e. the device actually gets used). Add a new 'sqq' member, the bind-time sequence number. It operates in parallel to the old values for now. All devices get a valid sqq value, i.e. it is never -1. Drop an #ifdef while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Update uclass_find_next_free_req_seq() argsSimon Glass2020-12-183-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this is passed a uclass ID and it has to do a lookup. The callers all have the uclass pointer, except for the I2C uclass where the code will soon be deleted. Update the argument to a uclass * instead of an ID since it is more efficient. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Avoid accessing seq directlySimon Glass2020-12-1879-153/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-13250-1151/+1145
| | | | | | | | | | | | | | | | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-27 16:20:24 +0000