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| * power: pmic_pca9450: fix PCA9450A I2C addressSébastien Szymanski2020-07-161-20/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Quoting Ye Li from NXP: "We have confirmed with PMIC team, 0x35 is used only on early chips and not used any more. 0x25 is the final address." Fix it by merging power_pca9450a_init and power_pca9450b_init into one function power_pca9450_init. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Ye Li <ye.li@nxp.com>
| * gpio: mxc_gpio: Improve to use ofdata_to_platdataYe Li2020-07-161-27/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Current mxc_gpio DM driver allocates the platdata in bind function to handle both OF_CONTROL enabled case and disabled case. This implementation puts the devfdt_get_addr in bind, which introduces much overhead especially in board_f phase. Change the driver to a common way for handling the cases by using ofdata_to_platdata and using DM framework to allocate platdata. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * misc: scu_api: Add SCFW API to get the index of boot container setYe Li2020-07-161-0/+25
| | | | | | | | | | | | | | | | | | | | Add SCFW API sc_misc_get_boot_container to get current boot container set index. The index value returns 1 for primary container set, 2 for secondary container set. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * spi: fsl_qspi: Support to use full AHB space on i.MXYe Li2020-07-162-24/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX platforms provide large AHB mapped space for QSPI, each controller has 256MB. However, current driver only maps small size (AHB buffer size) of AHB space, this implementation causes i.MX failed to boot M4 with QSPI XIP image. Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX) to address above problem. When the config is set: 1. Full AHB space is divided to each CS. 2. A dedicated LUT entry is used for AHB read only. 3. The MODE instruction in LUT is replaced to standard ADDR instruction 4. The address in spi_mem_op is used to SFAR and AHB read Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
| * spi: fsl_qspi: Add support for i.MX7ULPYe Li2020-07-161-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
| * clk: imx8m: drop clk settingsPeng Fan2020-07-142-68/+0
| | | | | | | | | | | | | | We use non-dm code to configure the clk settings in order to simplify dm clk driver in future, so remove the duplicated code from clk driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx8mp: Update imx8mp ccf clock driverYe Li2020-07-141-0/+52
| | | | | | | | | | | | | | | | Add clocks for FEC and flexspi, and add set parent clock callback, so DTS can assign clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx8mm/8mn: Add USB clocksYe Li2020-07-142-0/+37
| | | | | | | | | | | | | | | | Add USB relevant clocks to support usb clock settings for both DM USB host and gadget drivers Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: clk-imx8mn: Update clock tree and support set parentYe Li2020-07-141-0/+56
| | | | | | | | | | | | | | | | Add set clock parent support. Add ENET and flexspi related clocks to support assigned clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx8mm: Add qspi clockPeng Fan2020-07-141-0/+7
| | | | | | | | | | | | Add qspi clock Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx8mm: fix clk set parentPeng Fan2020-07-141-1/+4
| | | | | | | | | | | | | | Fix clk set parent, so we could still have correct clocks after parent changing. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: power-domain: use arm_smccc_smcPeng Fan2020-07-141-4/+6
| | | | | | | | | | | | Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8: fuse: use arm_smccc_smcPeng Fan2020-07-141-7/+12
| | | | | | | | | | | | Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * pinctrl: imx5: move soc info to data sectionPeng Fan2020-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * pinctrl: imx8m: move soc info to data sectionPeng Fan2020-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * pinctrl: imx7: move soc info to data sectionPeng Fan2020-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issueOliver Chen2020-07-143-0/+174
| | | | | | | | | | | | | | | | | | | | Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * drivers: ddr: imx8mp: Add inline ECC feature supportSherry Sun2020-07-142-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8mJacky Bai2020-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | The 'selfref_en' should be bit'0', so correct the setting to enable the auto self-refresh. Reviewed-by: Jian Li <jian.li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * driver: ddr: imx: skip ddr_ss_gpr config on imx8mnJacky Bai2020-07-141-1/+1
| | | | | | | | | | | | | | | | There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting this register on i.MX8MN. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | Merge tag 'mmc-7-24-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini2020-07-152-8/+49
|\ \ | | | | | | | | | | | | | | | - Correct mmc_spi check condition - Generate R1/R2/R1b response - Read SSR for SD SPI
| * | mmc_spi: generate R1b response for erase and stop transmission commandPragnesh Patel2020-07-141-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the SD physical layer specification version 7.10, erase command (CMD38) and stop transmission command (CMD12) will generate R1b response. R1b = R1 + busy signal A non-zero value after the R1 response indicates card is ready for next command. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | mmc: mmc_spi: Generate R1 response for erase block start and end addressPragnesh Patel2020-07-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erase block start address (CMD32) and erase block end address (CMD33) command will generate R1 response for mmc SPI mode. R1 response is 1 byte long for mmc SPI, so assign 1 byte as a response for this commands. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | mmc: mmc_spi: Read R2 response for send status command - CMD13Pragnesh Patel2020-07-141-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Send status command (CMD13) will send R1 response under SD mode but R2 response under SPI mode. R2 response is 2 bytes long, so read 2 bytes for mmc SPI mode Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | mmc: read ssr for SD spiPragnesh Patel2020-07-142-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The content of ssr is useful only for erase operations. This saves erase time. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | mmc: mmc_spi: generate R1 response for different mmc SPI commandsPragnesh Patel2020-07-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R1 response is 1 byte long for mmc SPI commands as per the updated physical layer specification version 7.10. So correct the resp and resp_size for existing commands Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | mmc: mmc_spi: correct the while conditionPragnesh Patel2020-07-141-1/+3
| |/ | | | | | | | | | | | | | | | | | | | | When variable i will become 0, while(i--) loop breaks but variable i will again decrement to -1 because of i-- and that's why below condition "if (!i && (r != resp_match_value)" will never execute, So doing "i--" inside of while() loop solves this problem. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* | mmc: omap_hsmmc: Set 3.3V for IO voltage on all placesPali Rohár2020-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit commit d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage") was changed 3.0V IO voltage to 3.3V but it was not done on all places in omap_hsmmc driver. That commit broke eMMC support on Nokia N900. This patch fixes that problematic commit and changes 3.0V to 3.3V on all remaining places in omap_hsmmc driver. Fixes: d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage") Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
* | net: ti: am65-cpsw-nuss: Update driver to use kernel DTVignesh Raghavendra2020-07-131-1/+1
| | | | | | | | | | | | | | Kernel DT has CPSW ports under ethernet-ports subnode. Update the driver to look for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | net: ti: am65-cpsw-nuss: Set ALE default thread enableVignesh Raghavendra2020-07-131-0/+6
| | | | | | | | | | | | | | Force default thread to be used for RX as ALE is anyways set to Bypass mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | net: ti: am65-cpsw-nuss: Remove dead codeVignesh Raghavendra2020-07-131-7/+0
| | | | | | | | | | | | MDIO node is not referenced further, therefore drop the dead code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | dma: ti: k3-udma: Switch to k3_ringacc_request_rings_pairVignesh Raghavendra2020-07-131-37/+15
| | | | | | | | | | | | | | | | | | | | We only request ring pairs via K3 DMA driver, switch to use the new k3_ringacc_request_rings_pair() to simplify the code. As a good side effect, all boot stages now use exposed RING mode which avoid maintaining proxy mode for 32 bit R5 core. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | dma: ti: k3-udma: Move RX descriptor ring entries to rflow structVignesh Raghavendra2020-07-131-24/+28
| | | | | | | | | | | | | | In K3 UDMA architecture, RX rings are associated with RX flows rather than RX channels, therefore move the ring pointers to udma_rflow struct Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | dma: ti: k3-udma: Introduce udma_chan_config structVignesh Raghavendra2020-07-131-89/+108
| | | | | | | | | | | | | | | | Encapsulate channel configuration in a separate struct so as to ease resetting of these fields with memset() and also to increase readability of the code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | soc: ti: k3-ringacc: Separate soc specific initializationVignesh Raghavendra2020-07-131-9/+40
| | | | | | | | | | | | | | In preparation of adding more K3 SoCs, separate soc specific initialization add a SoC specific initialization hook. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | soc: ti: k3-ringacc: Add an API to request pair of ringsVignesh Raghavendra2020-07-131-0/+23
| | | | | | | | | | | | | | | | | | | | Add new API k3_ringacc_request_rings_pair() to request pair of rings at once, as in the most case Rings are used with DMA channels which required to request pair of rings - one to feed DMA with descriptors (TX/RX FDQ) and one to receive completions (RX/TX CQ). This will allow to simplify Ringacc API users. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | soc: ti: k3-ringacc: Move state tracking variables under a structVignesh Raghavendra2020-07-131-43/+46
| | | | | | | | | | | | | | | | Move the free, occ, windex and rinfex under a struct. We can use memset to zero them and it will allow a cleaner way to extend the variables for duplex rings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | dma: ti: k3-udma: Update driver to use static endpoint DataVignesh Raghavendra2020-07-132-43/+103
| | | | | | | | | | | | | | | | | | | | | | | | Update driver to use static PSIL endpoint Data instead of DT. This will allow DT bindings to be in sync with kernel's DT. Note that this patch breaks networking and OSPI boot as driver changes are not backward compatible with existing DT. Subsequent commit will update the DT to make it compatible with updated driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | dma: ti: Add static PSIL endpoint informationVignesh Raghavendra2020-07-137-0/+295
|/ | | | | | | | | | | | Much of PSIL endpoint configuration for a given SoC can be known at compile time, therefore pass them for platform specific data instead of DT. Add per SoC's specific PSIL endpoint data. This is to bring driver in sync with upstream DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini2020-07-115-286/+67
|\ | | | | | | | | | | | | - Enable DM_SPI on siemens omap boards (Jagan) - Dropped some non-dm supported omap3 boards (Jagan) - Dropped non-dm code in omap3 spi driver (Jagan) - Dropped non-dm code in kirkwood spi driver (Bhargav)
| * spi: kirkwood: Drop nondm codeBhargav Shah2020-07-102-129/+19
| | | | | | | | | | | | | | | | Drop the nondm code from kirkwood_spi.c since there is no board or any other code using for it. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Enable QE bit for ISSI flash in case of SFDPPragnesh Patel2020-07-091-3/+4
| | | | | | | | | | | | | | | | | | | | Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: add support for all spi modes with soft spiJohannes Holland2020-07-091-11/+37
| | | | | | | | | | | | | | | | | | | | The spi bitbanging driver did not implement all spi modes properly. Add code to support all spi modes, honoring soft_spi_set_mode() and defaulting to spi mode 0. Previously, CPHA was implemented inversely (defaulting to CPHA=1) and CPOL=1 was hardcoded. Signed-off-by: Johannes Holland <johannes.holland@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: omap3: Drop nondm codeJagan Teki2020-07-092-143/+7
| | | | | | | | | | | | | | Now all boards are using this omap3 spi driver in dm model, so drop the nondm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge tag 'uniphier-v2020.10' of ↵Tom Rini2020-07-119-44/+191
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.10 - remove workaround for Cortex-A72 - increase U-Boot proper size to 2MB - sync DT with Linux - add system bus controller driver - improve serial driver - add reset assertion to Denali NAND driver
| * | mtd: nand: raw: denali: Wait for reset completion statusLey Foon Tan2020-07-113-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed delay 200us is not working in certain platforms. Change to poll for reset completion status to have more reliable reset process. Controller will set the rst_comp bit in intr_status register after controller has completed its reset and initialization process. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: nand: raw: denali: Assert reset before deassertLey Foon Tan2020-07-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Always put the controller in reset, then take it out of reset. This is to make sure controller always in reset state in both SPL and proper Uboot. This is preparation for the next patch to poll for reset completion (rst_comp) bit after reset. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | serial: uniphier: enable FIFOMasahiro Yamada2020-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This UART controller is integrated with a FIFO. Enable it. You can put the next character into the FIFO while the transmitter is sending out the current character. This works slightly faster. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | serial: uniphier: flush transmitter before changing hardware settingsMasahiro Yamada2020-07-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Ensure the transmitter is empty when chaining the baudrate or any hardware settings. If a character is remaining in the transmitter, the console will be garbled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | serial: uniphier: use register macros instead of structureMasahiro Yamada2020-07-111-43/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After all, I am not a big fan of using a structure to represent the hardware register map. You do not need to know the entire register map. Add only necessary register macros. Use FIELD_PREP() instead of maintaining a pair of shift and mask. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit (git 2.34.1) at 2025-10-01 21:35:44 +0000