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* pci: Add PCI controller driver for OcteonTX / TX2Suneel Garapati2020-08-253-0/+373
| | | | | | | | | Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* ata: ahci: Add BAR index quirk for Cavium PCI SATA deviceSuneel Garapati2020-08-251-0/+15
| | | | | | | | For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0 instead of BAR5. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: pci-uclass: Check validity of ofnodeSuneel Garapati2020-08-251-3/+7
| | | | | | | | Add check if the referenced ofnode is valid. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Add support for Alternate-RoutingID capabilitySuneel Garapati2020-08-252-0/+35
| | | | | | | | | If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Add VF BAR map support for Enhanced AllocationSuneel Garapati2020-08-251-5/+62
| | | | | | | | | Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Add support for Single-Root I/O VirtualizationSuneel Garapati2020-08-252-0/+124
| | | | | | | | | | | | | | | | SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Add support for Enhanced Allocation in BridgesSuneel Garapati2020-08-251-6/+18
| | | | | | | | | If Enhanced Allocation capability is present in bridges, use it to read the fixed sub-ordinate bus number. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Add multi entry support for memory regionsSuneel Garapati2020-08-252-3/+16
| | | | | | | | | | Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Make DT subnode parse optionalSuneel Garapati2020-08-251-1/+2
| | | | | | | | | | Parse subnode DT properties only if parent node is valid. Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode from dev_for_each_subnode. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Fix incorrect argument in map_physmemSuneel Garapati2020-08-251-2/+2
| | | | | | | | | Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar(). Additinally minor spelling correction. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
* pci: pci-uclass: Dynamically allocate the PCI regionsStefan Roese2020-08-251-6/+8
| | | | | | | | | | | | | | | Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
* pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always setStefan Roese2020-08-251-16/+1
| | | | | | | | | | | Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for all boards. Hence we can remove the conditional compilation and the code path that will never get compiled. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Add API to read PCI bus-range propertyStefan Roese2020-08-251-0/+17
| | | | | | | Add dev_read_pci_bus_range() to read bus-range property values Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-clk-24Aug2020' of ↵Tom Rini2020-08-2410-13/+88
|\ | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add CCF clocks definitions for iMX6Q enet (ETH) - Several fixes for CCF framework - the most notable is the one, which adds get_rate helper to clk-mux.c - Improvements for clk command - better visibility and alignment.
| * clk: ccf: Add missing #include <dm/uclass.h> to clk-mux.cLukasz Majewski2020-08-241-0/+1
| | | | | | | | | | | | | | | | After adding custom get_rate helper function it was necessary to include <dm/uclass.h> to avoid warnings about missing uclass_get_device_by_name. Signed-off-by: Lukasz Majewski <lukma@denx.de> Series-to: u-boot
| * clk: ccf: mux: change the get_rate helperDario Binacchi2020-08-241-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | The previous version of the get_rate helper does not work if the mux clock parent is changed after the probe. This error has not been detected because this condition has not been tested. The error occurs because the set_parent helper does not change the parent of the clock device but only the clock selection register. Since changing the parent of a probed device can be tricky, the new version of the get_rate helper provides the rate of the selected clock and not that of the parent. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ccf: mux: fix access to the sandbox registerDario Binacchi2020-08-241-0/+8
| | | | | | | | | | | | | | | | The tests developed for the mux clock are run on the sandbox. They don't call the clk_mux_set_parent routine and therefore they do not detect this error. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ccf: mux: fix typoDario Binacchi2020-08-241-1/+1
| | | | | | | | | | | | Close the opening bracket. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ccf: mux: change include orderDario Binacchi2020-08-241-4/+4
| | | | | | | | | | | | Apply u-boot coding style on include files order. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: fix the console output of clk_registerDario Binacchi2020-08-241-5/+5
| | | | | | | | | | | | | | The parent->name variable can be used only in case the uclass_get_device_by_name routine returns successfully. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: set flags in the ccf registration routinesDario Binacchi2020-08-246-1/+7
| | | | | | | | | | | | | | | | | | The top-level framework flags are passed as parameter to the common clock framework (ccf) registration routines without being used. Checks of the flags setting added by the patch have been added in the ccf test. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * dm: test: clk: add the test for the ccf gated clockDario Binacchi2020-08-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | Unlike the other clock types, in the case of the gated clock, a new driver has been developed which does not use the registering routine provided by the common clock framework. The addition of the ecspi0 clock to sandbox therefore allows testing the ccf gate clock. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clockLukasz Majewski2020-08-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide PTP clock. On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux kernel's CCF. Code in this change models the simplest case when enet reference clock is generated from 'osc' clock. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * clk: imx: Add support for pllv3 enet clockLukasz Majewski2020-08-241-0/+25
| | | | | | | | | | | | | | | | | | | | This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * clk: imx6: Add definition for IMX6QDL_CLK_ENET clockLukasz Majewski2020-08-241-0/+1
| | | | | | | | | | | | | | | | | | | | After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide IMX6QDL_CLK_ENET. This change defines the missing clock in i.MX6Q's CCF. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * clk: ICS8N3QV01 remove superfluous codeHeinrich Schuchardt2020-08-241-1/+0
| | | | | | | | | | | | | | | | | | | | Do not calculate a unused value of n which is overwritten in both branches of the subsequent if statement. Identified by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* | Merge tag 'dm-pull-22aug20' of ↵Tom Rini2020-08-2323-39/+65
|\ \ | |/ |/| | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm replace devfdt_get_addr_ptr() with dev_read_addr_ptr() binman fixes for portage various minor fixes 'bind' command improvements
| * treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()Masahiro Yamada2020-08-2218-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To help this tedious work, this commit converts devfdt_get_addr_ptr() to dev_read_addr_ptr() by coccinelle. I also removed redundant casts because dev_read_addr_ptr() returns an opaque pointer. To generate this commit, I ran the following semantic patch excluding include/dm/. <smpl> @@ type T; expression dev; @@ -(T *)devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) @@ expression dev; @@ -devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ata: mvebu: use dev_read_addr() to get base addressMasahiro Yamada2020-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | It is strange to use devfdt_get_addr_ptr(), then cast the pointer back to ulong because you could use devfdt_get_addr() without casting. Convert it to dev_read_addr(), which is capable to CONFIG_OF_LIVE. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * gpio: at91: use dev_read_addr() to get base addressMasahiro Yamada2020-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | It is strange to use devfdt_get_addr_ptr(), then cast the pointer back to uint32 because you could use devfdt_get_addr() without casting. Convert it to dev_read_addr(), which is capable to CONFIG_OF_LIVE. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: core: Fix devfdt_get_addr_ptr return valueOvidiu Panait2020-08-226-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | According to the description of devfdt_get_addr_ptr, this function should return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE. Fix this by making devfdt_get_addr_ptr return NULL on failure, as described in the function comments. Also, update the drivers currently checking (void *)FDT_ADDR_T_NONE to check for NULL. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: phy: add driver_data for bind test cmdPatrice Chotard2020-08-221-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver data to existing compatible string "sandbox,phy". Add an additional compatible string without driver_data This will verify that bind command parses, finds and passes the correct driver data to device_bind_with_driver_data() by using driver_data in the second sandbox_phy_ids table entry. In sandbox_phy_bind() a check is added to validate driver_data content. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: fix ofnode_read_addr/size_cells()Heinrich Schuchardt2020-08-221-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of the live tree ofnode_read_addr_cells() and ofnode_read_size_cells() return the #address-cells and #size-cells defined in the parent node. With the patch the same is done for a non-live tree. The only consumer of these functions is currently the CFI flash driver. This patch fixes the incorrect parsing of the device tree leading to 'saveenv' failing on qemu_arm64_defconfig. For testing qemu-system-aarch64 has to be called with -drive if=pflash,format=raw,index=1,file=envstore.img to provide the flash memory. envstore.img must be 64 MiB large. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* | Convert CONFIG_SPLASH_SCREEN et al to KconfigSimon Glass2020-08-231-0/+85
|/ | | | | | | | | | This converts the following to Kconfig: CONFIG_SPLASH_SCREEN CONFIG_SPLASH_SCREEN_ALIGN CONFIG_SPLASHIMAGE_GUARD CONFIG_SPLASH_SOURCE Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'xilinx-for-v2020.10-rc3' of ↵Tom Rini2020-08-2011-83/+77
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.10-rc3 - Fix fdtfile variable setup - Fix bootm_*/fdt_high/initrd_high variables handling - Fix Kconfig dependencies for Xilinx drivers - Fix booting u-boot from lowest memory - Fix firmware payload argument count for Versal - Fix dfu configurations - Fix mio_bank property handling - Fix and align code around ID detection - Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG - Simplify logic around reading MAC from eeprom - Decrease malloc length for zynqmp mini qspi - Enable preboot for ZynqMP and Versal i2c: - Fix i2c eeprom partitions handling mmc: - Fix logic around HS mode enabling and use proper functions
| * clk: versal: Move pm_query_id out of clock driverMichal Simek2020-08-201-17/+0
| | | | | | | | | | | | | | | | | | There is no reason to have firmware specific structure in clock driver. Move it to generic location and also initialize enum values which is based on https://lore.kernel.org/linux-arm-kernel/20200318125003.GA2727094@kroah.com/ recommended way to go to make sure that values guaranteed by compiler. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: sdhci: Use upper/lower_32_bits macrosMichal Simek2020-08-201-4/+4
| | | | | | | | | | | | | | Instead of recasting and shifting use macros which are designed for taking upper/lower 32bit value from 64bit variable. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: sdhci: Enable high speed conditional on the corresponding bitFaiz Abbas2020-08-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | The capabilities register has a field to indicate whether the host supports high speed mode or not. Add high speed host_caps based on this bit instead of enabling it by default. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Michal Simek <michal.simek@xilnx.com> Tested-by: Michal Simek <michal.simek@xilnx.com> (zcu104 with sdhci-caps-mask = <0 0x200000>;)
| * xilinx: zynqmp: fix incorrect map not align with IPI HWIbai Erkiaga2020-08-201-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Current IPI module register description is not align with IPI HW. The registers with the wrong offset are not used so it does not cause real issues. This patch aligns the register description. Additionally comments added to explain why recv function does not check any flag prior copying rx data. Fixes: 660b0c77d816 ("mailbox: zynqmp: ipi mailbox driver") Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: merge firmware calls for EL2 and EL3Ibai Erkiaga2020-08-201-41/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch merges ZynqMP firmware calls under xilinx_pm_request in order to make trainsparent the EL. Calls at EL3 are send through IPI messages and EL2 through SMC calls. The EL2 call uses fixed payload and arg size as the EL3 call. The firmware is capable to handle PMUFW_PAYLOAD_ARG_CNT bytes but the firmware API is limited by the SMC call size. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: synchronize firmware call return payloadIbai Erkiaga2020-08-201-1/+1
| | | | | | | | | | | | | | | | | | Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the firmware driver. Additionally fixes payload buffer declarations without macro usage Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq: Fix default value for xlnx,mio-bankMichal Simek2020-08-201-1/+1
| | | | | | | | | | | | | | | | DT binding is saying that default value is 0 not -1 that's why fix it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Peng Fan <peng.fan@nxp.com>
| * xilinx: Fix xlnx,mio_bank propertyMichal Simek2020-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | s/xlnx,mio_bank/xlnx,mio-bank/g DT binding is describing mio-bank not mio_bank that's why fix all DTSes and also driver itself. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Peng Fan <peng.fan@nxp.com>
| * i2c: eeprom: Use reg property instead of offset and sizeMichal Simek2020-08-201-7/+8
| | | | | | | | | | | | | | | | Remove adhoc dt binding for fixed-partition definition for i2c eeprom. fixed-partition are using reg property instead of offset/size pair. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek2020-08-204-7/+6
| | | | | | | | | | | | | | | | | | Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | ahci: mediatek: add ahci driverFrank Wunderlich2020-08-193-0/+139
| | | | | | | | | | | | | | | | add AHCI driver ported from linux https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | reset: add basic reset controller for pciesysFrank Wunderlich2020-08-191-0/+15
| | | | | | | | | | | | bind reset controller to pciesys Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | phy: mtk-tphy: add PHY_TYPE_SATAFrank Wunderlich2020-08-191-0/+105
| | | | | | | | | | | | | | add support for PHY_TYPE_SATA to Mediateks TPHY driver Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | PCI: mediatek: Add PCIe support for MT7622Chuanjia Liu2020-08-191-3/+459
| | | | | | | | | | | | | | This patch adds PCIe support for the Mediatek MT7622 SOC. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Signed-off-by: Henry Yen <henry.yen@mediatek.com>
* | clk: mediatek: add pciesys support for MT7622 SoCChuanjia Liu2020-08-191-0/+54
| | | | | | | | | | | | | | | | This patch adds pciesys support in clock driver for MediaTek MT7622 SoC. Signed-off-by: Henry Yen <henry.yen@mediatek.com> Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
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