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* spi: ti_qspi: Drop non DM codeVignesh Raghavendra2019-04-173-200/+46
| | | | | | | | | | | Now that all boards using TI QSPI have moved to DM and DT, drop non DM code completely. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [jagan: update MIGRATION.txt, rebase config_whitelist.txt] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2019-04-1412-53/+107
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/dts/armada-385-amc.dts arch/arm/dts/armada-xp-theadorable.dts arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi Signed-off-by: Tom Rini <trini@konsulko.com>
| * mtd: spi-nor-ids: Add Gigadevice gd25lq128 IDNeil Armstrong2019-04-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: spi: Read default speed and mode values from DTPatrick Delaunay2019-04-122-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch update the behavior introduced by commit 96907c0fe50a ("dm: spi: Read default speed and mode values from DT") In case of DT boot, don't read default speed and mode for SPI from CONFIG_* but instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Remove also use in boards of the value speed=0 (no more supported) for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0. DT values will be always used when available (full DM support of SPI slave with available DT node) even if speed and mode are requested; for example in splash screen support (in splash_sf_read_raw) or in SPL boot (in spl_spi_load_image). The caller of spi_get_bus_and_cs() no more need to force speed=0. But the current behavior don't change if the SPI slave is not present (device with generic driver is created automatically) or if platdata is used (CONFIG_OF_PLATDATA). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi: Replace ad-hoc default implementation with spi_mem_opMarek Vasut2019-04-121-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the ad-hoc erase operation implementation with a simple spi_mem_op implementation of the same functionality. This is a minor optimization and removal of the ad-hoc code. This however also changes the behavior of the execution of the erase opcode from two separate transfer requests to the SPI NOR driver to one transfer request to the SPI NOR driver. The former was how U-Boot behaved before the SPI NOR framework was imported and the later was introduced by the SPI NOR framework. The former is more optimal, so keep that. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Ashish Kumar <Ashish.kumar@nxp.com>
| * spi: fsl_dspi fix to stop extra transmissionsJared Bents2019-04-121-4/+26
| | | | | | | | | | | | | | | | | | | | Update to prevent a byte of zeros being transmitted between each byte in the tx buffer when providing both a tx buffer and a rx buffer. Signed-off-by: Jared Bents <jared.bents@rockwellcollins.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: spi-mem: Check if exec_op function is set before calling itBernhard Messerklinger2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | Add check if exec_op is set before calling it. At the moment it is called unconditionally, which leads to a crash if it is not set correctly. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: fix Coverity integer handling issueMiquel Raynal2019-04-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A Coverity robot reported an integer handling issue (OVERFLOW_BEFORE_WIDEN) in the potentially overflowing expression: (mtd_div_by_ws(mtd->size, mtd) - mtd_div_by_ws(offs, mtd)) * mtd_oobavail(mtd, ops) While such overflow will certainly never happen due to the numbers handled, it is cleaner to fix this operation anyway. The problem is that all the maths include 32-bit quantities, while the result is stored in an explicit 64-bit value. As maxooblen will just be compared with a size_t, let's change the type of the variable to a size_t. This will not fix anything but will clarify a bit the situation. Then, do an explicit cast to fix Coverity warning. Addresses-Coverity-ID: 184180 ("Integer handling issues") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: spi: Add Macronix MX66U2G45F deviceMarek Vasut2019-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add Macronix MX66U2G45F flash device description. This is a 256 MiB part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Vignesh R <vigneshr@ti.com> [jagan: use 'g' instead of 'f' in flash name] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: sf_probe: remove spi-flash compatibleNeil Armstrong2019-04-121-1/+0
| | | | | | | | | | | | | | | | | | | | Now the "spi-flash" compatible has been removed in the DTS files, remove this compatible from sf_probe to finally use the Linux "jedec,spi-nor" compatible. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * mtd: add spi flash id s25fl064lHeiko Schocher2019-04-121-0/+1
| | | | | | | | | | | | | | | | Add support for SPANSION s25fl064l Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Vignesh R <vigneshr@ti.com>
| * mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux versionStefan Roese2019-04-121-32/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support with the latest Linux version (v5.0-rc3) plus the chip supported posted on the MTD list. Only the currently in U-Boot available chip is supported with this sync. The changes for the GD5F1GQ4UExxG are: - Name of NAND device changed to better reflect the real part - OOB layout changed to only reserve 1 byte for BBT - Use ECC caps 8bits/512bytes instead of 8bits/2048bytes - Enhanced ecc_get_status() function to determine and report a more fine grained bit error status Signed-off-by: Stefan Roese <sr@denx.de> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Add quad write supportLey Foon Tan2019-04-123-3/+8
| | | | | | | | | | | | | | | | | | | | Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dmTom Rini2019-04-137-108/+92
|\ \ | | | | | | | | | | | | | | | fdtdec tests and improvements for carve-outs pinctrl race-condition fix various other fixes in sandbox, sound, mkimage, etc.
| * | dm: remove unused function dm_fdt_pre_relocPatrick Delaunay2019-04-111-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | The function dm_ofnode_pre_reloc should be used instead of the function dm_fdt_pre_reloc and avoid duplicated code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+2
| | | | | | | | | | | | | | | | | | | | | Prepare to remove dm_fdt_pre_reloc function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | clk: at91: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | Prepare to remove dm_fdt_pre_reloc Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | core: ofnode: Fix ASAN-reported stack-buffer-overflow in of_get_addressEugeniu Rosca2019-04-111-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2019.04-rc3 sandbox U-Boot fails to boot when compiled with -fsanitize=address and linked against -lasan, reporting [1]. Git bisecting shows that the issue is contributed by v2019.01 commit 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function"). The root cause seems to be the mismatch between sizeof(u64) and sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the size argument of both of_get_address() and fdtdec_get_addr_size_fixed() is optional, we can pass NULL in its place, avoiding the problem. [1] Backtrace reported by ASAN (gcc 8.1.0): $> ./u-boot -d arch/sandbox/dts/sandbox.dtb [..] Reviewed-by: Simon Glass <sjg@chromium.org> ================================================================= ==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffcc2331140 at pc 0x0000004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70 WRITE of size 8 at 0x7ffcc2331140 thread T0 #0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154 #1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263 #2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422 #3 0x4dccd8 in device_probe drivers/core/device.c:407 #4 0x753170 in eth_initialize net/eth-uclass.c:428 #5 0x47d9bf in initr_net common/board_r.c:557 #6 0x6bcfa7 in initcall_run_list lib/initcall.c:30 #7 0x47e1fe in board_init_r common/board_r.c:859 #8 0x4060e5 in main arch/sandbox/cpu/start.c:356 #9 0x7fb8d135482f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f) #10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8) Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame #0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255 This frame has 3 object(s): [32, 36) 'size' <== Memory access at offset 32 partially overflows this variable [96, 100) 'flags' [160, 168) 'node' HINT: this may be a false positive if your program uses some custom stack unwind mechanism or swapcontext (longjmp and C++ exceptions *are* supported) SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154 in of_get_address Shadow bytes around the buggy address: 0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2 0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00 =>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2 0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3 0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3 0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb ==10998==ABORTING 'To' list: git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \ sed 's/.*-by: //' | sort | uniq -c | sort -rn 10 Simon Glass <sjg@chromium.org> 3 Mario Six <mario.six@gdsys.cc> 2 Martin Fuzzey <mfuzzey@parkeon.com> 2 Marek Vasut <marek.vasut+renesas@gmail.com> 1 Tom Rini <trini@konsulko.com> 1 Masahiro Yamada <yamada.masahiro@socionext.com> 1 Keerthy <j-keerthy@ti.com> 1 Jens Wiklander <jens.wiklander@linaro.org> 1 Bin Meng <bmeng.cn@gmail.com> Fixes: 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
| * | sysreset: use syscon_regmap_lookup_by_phandlePatrick Delaunay2019-04-111-13/+2
| | | | | | | | | | | | | | | | | | | | | Use the new function syscon_regmap_lookup_by_phandle() to simplify the code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | syscon: update syscon_regmap_lookup_by_phandlePatrick Delaunay2019-04-111-24/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the function syscon_regmap_lookup_by_phandle() introduced by commit 6c3af1f24e4b ("syscon: dm: Add a new method to get a regmap from DTS") to have Linux-compatible syscon API. Same modification than commit e151a1c288bd ("syscon: add Linux-compatible syscon API") solves issue when the node identified by the phandle has several compatibles and is already bound to a dedicated driver. See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon interface from platform devices"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind()Patrick Delaunay2019-04-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some binding define child node gpio-controller without compatible property. This patch avoid to bind the pinconfig uclass to these node. For example, the binding for st,stm32-pinctrl (./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl) but without compatible (as it is not mandatory). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: pinctrl: Avoid race condition on probe for UCLASS_PINCTRLPatrice Chotard2019-04-111-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of system with several pin-controller device, probe the first UCLASS_PINCTRL by seq number (defined by alias) to avoid race condition with I2C PINCONTROL driver for GPIO expander (GPIO expander need I2C bus, I2C driver need PINCONFIG). Signed-off-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().Christoph Muellner2019-04-111-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. As noted in the comment, the function pinctrl_decode_pin_config_dm() only served as a temporary solution. Since the function has no users anymore, we can remove it again. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: remove pre reloc properties in SPL and TPL device treePatrick Delaunay2019-04-112-24/+23
| |/ | | | | | | | | | | | | | | | | | | | | | | | | We can remove the pre reloc property in SPL and TPL device-tree: - u-boot,dm-pre-reloc - u-boot,dm-spl - u-boot,dm-tpl As only the needed node are kept by fdtgrep (1st pass). The associated function (XXX_pre_reloc) are simple for SPL/TPL: return always true. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mipsTom Rini2019-04-1313-51/+2209
|\ \ | | | | | | | | | | | | | | | | | | | | | - mt76xx: add USB support, small fixes - ath79: small fixes, add support for QCA9563 SoC and AP152 reference board - mscc: small fixes, add network support for JR2 and ServalT SoCs - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs - MIPS: fix redundant relocation of initrd images
| * | phy: Add USB PHY driver for the MT76x8 (7628/7688) SoCStefan Roese2019-04-123-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | net: Add MSCC ServalT network driver.Horatiu Vultur2019-04-123-0/+630
| | | | | | | | | | | | | | | | | | | | | | | | Add network driver for Microsemi Ethernet switch. It is present on ServalT SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | net: Add MSCC Jaguar2 network driver.Horatiu Vultur2019-04-123-0/+1083
| | | | | | | | | | | | | | | | | | | | | | | | Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * | gpio: bcm6345: allow this driver on ARCH_BCM63158Philippe Reynes2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | This IP is also used on some arm SoC, so we allow to use this driver on arch bcm63158. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * | gpio: bcm6345: allow this driver on ARCH_BCM6858Philippe Reynes2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | This IP is also used on some arm SoC, so we allow to use this driver on arch bcm6858. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * | gpio: bcm6345: switch to raw I/O functionsPhilippe Reynes2019-04-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | ag7xxx: add initial support for s17Rosy Song2019-04-121-16/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | S17 ethernet support is for QCA8337N, which used on AP152 (QCA9563) board. It is a 7 ports GbE switch. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more commit message for s17 Changes for v4-v5: - coding style cleanup
| * | dma: bcm6348: check if driver is enabled before send/recvÁlvaro Fernández Rojas2019-04-121-0/+6
| | | | | | | | | | | | | | | | | | This patch prevents errors when running tftpput. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * | net: mscc: ocelot: Fix reset of the physHoratiu Vultur2019-04-121-17/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | drivers: add ethernet support for qca953x in ag7xxx driverRosy Song2019-04-121-17/+186
| | | | | | | | | | | | Signed-off-by: Rosy Song <rosysong@rosinson.com>
| * | drivers: fix typo for pinctrl qca953xRosy Song2019-04-121-1/+1
| |/ | | | | | | Signed-off-by: Rosy Song <rosysong@rosinson.com>
* | Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-bootTom Rini2019-04-1219-1159/+2774
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stm32 patches for v2019.07-rc1 - Add trusted boot with TF-A for stm32mp1 - stm32mp1 dts files sync'ed with Linux version - add STM32MP1 Discovery boards (DK1 and DK2) - add STMFX gpio expander driver - misc improvement for stm3mp1 supports - rename stpmu1 to stpmic1 (official name) - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu) - add STM32 FMC2 NAND flash controller driver
| * | mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driverChristophe Kerello2019-04-123-0/+1104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
| * | spi: stm32_qspi: move to exec_opChristophe Kerello2019-04-122-383/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are facing issues in the driver since SPI NOR framework has moved on SPI MEM framework, and SPI NAND framework is not running properly with the current driver. To be able to solve issues met on SPI NOR Flashes and to be able to support SPI NAND Flashes, the driver has been reworked. We are now using exec_op ops instead of using xfer ops. Thanks to this rework, the driver has been successfully tested with: - mx66l51235l SPI NOR Flash on stm32f746 SOC - n25q128a SPI NOR Flash on stm32f769 SOC - mx66l51235l SPI NOR Flash on stm32mp1 SOC - mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
| * | pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverPatrick Delaunay2019-04-123-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on UCLASS_PINCTRL and UCLASS_GPIO. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * | stpmic1: add NVM update support in fuse commandPatrick Delaunay2019-04-122-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to read/update the non volatile memory of STPMIC1 (8 bytes-register at 0xF8 address) and allow access with fuse command (bank=1, word > 0xF8). For example: STM32MP> fuse read 1 0xf8 8 Reading bank 1: Word 0x000000f8: 000000ee 00000092 000000c0 00000002 Word 0x000000fc: 000000f2 00000080 00000002 00000033 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | pmic: stpmu1: add power switch off supportPatrick Delaunay2019-04-121-0/+46
| | | | | | | | | | | | | | | | | | | | | Add sysreset support, and support power switch off request, needed by poweroff command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stpmic1: update register namesPatrick Delaunay2019-04-121-57/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | power: rename stpmu1 to official name stpmic1Patrick Delaunay2019-04-126-292/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | power: stpmu1: rename files to stpmic1Patrick Delaunay2019-04-124-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Prepare file modification for kernel alignment and rename driver to stpmic1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | regulator: stpmu1: update buck1 rangePatrick Delaunay2019-04-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | SW impact for Rev 1.2 of STPMIC1 in U-Boot: Buck converters output voltage change for Buck1 => Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V (see STPMIC1 datasheet / chapter 5.3 Buck converters) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: add trusted boot with TF-APatrick Delaunay2019-04-122-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2019-04-125-11/+79
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| * | | misc: i2c_eeprom: add eeprom write supportBaruch Siach2019-04-111-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Write up to page size in each i2c transfer. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | misc: i2c_eeprom: support DT pagesize propertyBaruch Siach2019-04-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the page size from DT when available. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Heiko Schocher <hs@denx.de>
generated by cgit (git 2.34.1) at 2024-11-12 23:41:39 +0000