summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
...
| * | net: tsec: convert to use DM_MDIO when DM_ETH enabledHou Zhiqiang2020-09-241-33/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO. Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Reworked to fix gazerbeam config] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: fsl_mdio: Correct the MII management register block addressHou Zhiqiang2020-09-241-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MII management register block offset is different between gianfar and etsec2 compatible devices, this patch is to fix this issue by adding driver data for different compatible string. Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: fsl_mdio: Change to use virtual addressHou Zhiqiang2020-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use virtual address to access the MII block registers instead of physical address. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | phy: make phy_connect_fixed work with a null mdio busVladimir Oltean2020-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is utterly pointless to require an MDIO bus pointer for a fixed PHY device. The fixed.c implementation does not require it, only phy_device_create. Fix that. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | dm: add cells_count parameter in live DT APIs of_parse_phandle_with_argsPatrick Delaunay2020-09-222-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the live tree API ofnode_parse_phandle_with_args, the cell_count argument must be used when cells_name is NULL. But this argument is not provided to the live DT function of_parse_phandle_with_args even it is provided to fdtdec_parse_phandle_with_args. This patch adds support of the cells_count parameter in dev_ and of_node API to allow migration and support of live DT: - of_parse_phandle_with_args Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: syscon: typo aleradyHeinrich Schuchardt2020-09-221-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Fix typo: %s/alerady/already/. * Add missing 'the'. * Reformat a comment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | Merge branch '2020-09-14-generic-phy-error-trace' into nextTom Rini2020-09-215-19/+54
| |\ \ | | | | | | | | | | | | - Add error tracing messages to the generic PHY infrastructure
| | * | usb: musb-new: sunxi: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the dev_err/pr_err can be change to dev_dbg/pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | ata: dwc-ahci: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the pr_err can be change to pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | usb: host: ehci-hcd: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the pr_err can be change to pr_debug. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | usb: host: ohci: change trace level for phy errors managed by uclassPatrick Delaunay2020-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As the error message is now displayed by generic phy functions, the dev_err can be change to dev_dbg. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | phy: generic: add error trace to detect PHY issue in uclassPatrick Delaunay2020-09-081-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an error trace for PHY errors directly in generic phy functions provided by PHY uclass. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | Merge branch 'master' into nextTom Rini2020-09-216-28/+31
| |\ \ \ | | | |/ | | |/| | | | | Merge in v2020.10-rc5
| * | | usb: dwc3: Add Qualcomm DWC3 compatible stringRobert Marko2020-09-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0 ports. Qualcomm has some custom config registers on top of the generic ones, but for host mode these are not needed. So lets add the neccessary compatible string. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko2020-09-183-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | reset: Add IPQ40xx reset controller driverRobert Marko2020-09-183-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | IPQ40xx: Add SMEM supportRobert Marko2020-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is already existing driver for SMEM so lets enable it for IPQ40xx as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | net, qe: add DM support for QE UEC ethernetHeiko Schocher2020-09-1714-1/+2696
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add DM/DTS support for the UEC ethernet on QUICC Engine Block. Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com> Series-changes: 3 - revert: commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled") as now qe works with DM and DM_ETH support. - fix mailaddress from Holger Series-changes: 2 - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag Commit-notes: - I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS. - add the DM based qe uec driver under drivers/net/qe - Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes. - The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c - seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c END
| * | | powerpc, qe: add DTS support for parallel I/O portsHeiko Schocher2020-09-173-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
| * | | powerpc, qe: fix codingstyle issues for drivers/qeHeiko Schocher2020-09-177-972/+1040
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix Codingstyle for files in drivers/qe, remaining following check warnings: $ ./scripts/checkpatch.pl -f drivers/qe/uec.h CHECK: Macro argument reuse '_bd' - possible side-effects? +#define BD_ADVANCE(_bd, _status, _base) \ + (((_status) & BD_WRAP) ? (_bd) = \ + ((struct buffer_descriptor *)(_base)) : ++(_bd)) total: 0 errors, 0 warnings, 1 checks, 692 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h total: 0 errors, 0 warnings, 0 checks, 214 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uccf.c total: 0 errors, 0 warnings, 0 checks, 507 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec.c total: 0 errors, 0 warnings, 0 checks, 1434 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c total: 0 errors, 0 warnings, 0 checks, 927 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/qe.c CHECK: Lines should not end with a '(' +U_BOOT_CMD( total: 0 errors, 0 warnings, 1 checks, 830 lines checked Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | Merge tag 'ti-v2021.01-next' of ↵Tom Rini2020-09-153-91/+117
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next - Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
| | * | | spi: omap3_spi: Read platform data in ofdata_to_platdata()Faiz Abbas2020-09-151-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an ofdata_to_platdata() callback to access dts in U-boot and access all platform data in it. This prepares the driver for supporting both device tree as well as static platform data structures in SPL. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| | * | | arm: mach-omap2: am33xx: Add device structure for spiFaiz Abbas2020-09-151-69/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| | * | | spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failuresFaiz Abbas2020-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are devices which don't use OF_CONTROL or OF_PLATDATA but instead rely on statically defined platdata. Block dm_scan_fdt_dev() with both configs to avoid build failures under this condition. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * | | remoteproc: k3-r5: Add support for J7200 R5FsSuman Anna2020-09-151-10/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: Suman Anna <s-anna@ti.com>
| * | | | PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu2020-09-101-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
| * | | | clock:aspeed: Sync with Linux kernel clock header defineRyan Chen2020-09-091-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
| * | | | cosmetic: aspeed: ast2500: Rename clock headerRyan Chen2020-09-091-1/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| * | | Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of ↵Tom Rini2020-09-072-8/+3
| |\ \ \ | | |/ / | |/| | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
| | * | video: cfb_console.c: Use bi_dram[] values on all platformsStefan Roese2020-08-261-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All platforms support bi_dram[] since quite some time. Lets remove the and bi_memsize values completely. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always definedStefan Roese2020-08-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") & commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"), CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default). It makes no sense to still carry code that is guarded with "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes all these unreferenced code paths. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | | i2c: rcar_i2c: Fix i2c read/write errorsLad Prabhakar2020-10-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 7c8f821e5dde ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer") blindly called rcar_i2c_set_addr() with read argument always set to 1 during xfer which introduced read/write errors, whereas earlier rcar_i2c_read_common() called rcar_i2c_set_addr() with read set to 1 and rcar_i2c_write_common() called rcar_i2c_set_addr() with read set 0. Fixes: 7c8f821e5dde ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | | video: typo NormllyHeinrich Schuchardt2020-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | %s/Normlly/Normally/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | | mtd: fix typos in drivers/mtd/Kconfig, drivers/mtd/renesas_rpc_hf.cHeinrich Schuchardt2020-09-292-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo %s/interract/interact/ Use Samsung's capitalization of their trademarks %s/onenand/OneNAND/ %s/Hyperflash/HyperFlash/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add other Hyperflash cases as noted by Stefan] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | Merge tag 'u-boot-amlogic-20200928' of ↵Tom Rini2020-09-281-1/+2
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - fix RNG driver probe & linux EFI KASLR boot on GXL, GXM, G12A, G12B & SM1 based boards
| * | | | rng: meson: make core clock optionalNeil Armstrong2020-09-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes HWRNG support on Amlogic GXL, GXM, G12A, G12B & SM1 based boards dues to the lack of the core clock in the device tree. It was reported breaking EFI boot in the Linux EFI stub, because the EFI_RNG_PROTOCOL didn't check for the RNG device presence before installing itself. The Linux amlogic,meson-rng.yaml doesn't mandate the core clock, this the clock should be ignores if not present. Nevertheless, the clock should be present and this should be fixed on the Linux meson-gxl.dtsi & meson-g12-common.dtsi then synced with U-Boot. The change has been tested on a Khadas VIM3, which uses the common meson-g12-common.dtsi like the Odroid-C4 & Odroid-N2 in Scott's report, along with the RNG cmd. Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Scott K Logan <logans@cottsay.net> Fixes: bc40eb278b ("drivers/rng: add Amlogic hardware RNG driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Scott K Logan <logans@cottsay.net> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-09-257-26/+68
|\ \ \ \ \ | |/ / / / |/| | | | | | | | | | | | | | - Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on layerscape products
| * | | | pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2Hou Zhiqiang2020-09-241-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | net: pfe_eth: Remove non-DM code check from pfe_spi_flash_initKuldeep Singh2020-09-241-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DM_SPI_FLASH is only supported now with passing of driver conversion deadline from non-DM to DM model. Hence, it's safe to remove non-DM code check from pfe_spi_flash_init. Also use CONFIG_ENV_SPI_MODE and CONFIG_ENV_SPI_MAX_HZ instead of reading reading values from DT. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | net: pfe_eth: Fix resoure leak in pfe_spi_flash_initKuldeep Singh2020-09-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix Coverity issue: RESOURCE_LEAK. leaked_storage: Variable addr going out of scope leaks the storage it points to. Fixes: e0152dbed683 ("net: pfe_eth: Use spi_flash_read API to access flash memory") Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | driver: net: fm: add support for XFIMadalin Bucur2020-09-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the 10G ports that were working in XFI mode were described as using XGMII (as PHY_INTERFACE_MODE_XFI was not added at the time). Add the minimal changes required for the FMan code to support XFI. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | ls1012a, pfe_eth: Update probe to avoid resource leakChaitanya Sakinam2020-09-241-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PFE DDR addresses are now stored on to a stack varaiable rather dynamic allocation. Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | ls1012a, pfe_eth: correction in delay implementationChaitanya Sakinam2020-09-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | correction in delay implementation before we exit out of tx timeout. Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | drivers: net: phy: Use Aquantia driver for AQR113CMadalin Bucur2020-09-241-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for AQR113C PHY Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | drivers: net: ldpaa_eth: lx2160a: fix bug in checking if a DPMAC is enabledGrigore Popescu2020-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next DPMAC was always verified if it is enabled. In case of DPMAC@6, the DPMAC@7 is verified. As DPMAC@7 is disabled, DPMAC@6 will be considered disabled and not detected by uboot. Signed-off-by: Grigore Popescu <grigore.popescu@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | | pci: layerscape: Fix spurious writes and panicMichael Walle2020-09-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI root devices are layerscape PCIe controllers. Unfortunately, this is not true for the LS1028A. There is one additional static PCI root complex (this contains the networking devices) which has nothing to do with the layerscape PCIe controllers. On recent U-Boot versions this results in the following panic: "Synchronous Abort" handler, esr 0x96000044 elr: 000000009602fa04 lr : 000000009602f9f4 (reloc) elr: 00000000fbd73a04 lr : 00000000fbd739f4 x0 : 0080000002000101 x1 : 0000000000000000 x2 : 00000000fbde9000 x3 : 0000000000000001 x4 : 0000000000000000 x5 : 0000000000000030 x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0 x8 : 0000000000000002 x9 : 000000000000000c x10: 00000000ffffffe8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000000a2c x14: 00000000fbb3d2cc x15: 00000000ffffffff x16: 0000000000010000 x17: 0000000000000000 x18: 00000000fbb3fda0 x19: 0000000000000800 x20: 0000000000000000 x21: 00000001f0000000 x22: 0000000000000800 x23: 0000000000000009 x24: 00000000fbdc3c1b x25: 00000000fbdc28e5 x26: 00000000fbdcc008 x27: 00000000fbdc16e2 x28: 000000000f000000 x29: 00000000fbb3d3a0 Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814) Resetting CPU ... This bug already existed in former versions, but the spurious write was never trapped, because the destination address was a valid address (by pure luck). Make sure the PCI root is actually one of the expected PCIe layerscape controllers by matching its compatible string. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | | | arm64: a37xx: pci: Disable link training when unloading driverPali Rohár2020-09-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As required by PCI Express spec a delay for at least 100ms after de-asserting PERST# signal is needed before link training is enabled. Linux kernels prior to 5.8 version do not automatically disable link training before de-asserting PERST# signal, therefore this requirement is not fulfilled. Above requirement is needed for proper detection of some Compex PCIe WiFi cards. Otherwise Linux kernel cannot detect it. To allow using those PCIe cards with older Linux kernel versions booted by U-Boot compiled with U-Boot a37xx pci driver, disable link training in U-Boot when unloading this pci driver. Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver when booting Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | | | | mtd: spi-nor-ids: add support for Macronix mx25u12835f flashVladimir Vid2020-09-241-0/+1
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of Marvell A3700 boards use mx25u12835f, specifically uDPU and ESPRESSObin v7. Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> [a.heider: adapt commit message to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com>
* | | | pinmux: pic32: add SDHCI pin configJohn Robertson2020-09-231-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO pins used by the SDHCI controller need to be configured to allow the interface to work. Signed-off-by: John Robertson <john.robertson@simiatec.com>
* | | | mmc: pic32: Refresh PIC32 MMC driverJohn Robertson2020-09-231-36/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not always needed and can be disabled using a vendor specific DT property. Signed-off-by: John Robertson <john.robertson@simiatec.com>
generated by cgit (git 2.34.1) at 2025-10-01 10:32:32 +0000