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| | * | usb: xhci: convert to HCS_MAX_PORTS()Chunfeng Yun2020-10-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use HCS_MAX_PORTS(p) instead of ((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT) Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | usb: xhci: add quirks flag to support MediaTek xHCI 0.96Chunfeng Yun2020-10-013-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There some vendor quirks for MTK xHCI 0.96 host controller: 1. It defines some extra SW scheduling parameters for HW to minimize the scheduling effort for synchronous and interrupt endpoints. The parameters are put into reserved DWs of slot context and endpoint context. 2. Its TDS in Normal TRB defines a number of packets that remains to be transferred for a TD after processing all Max packets in all previous TRBs. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | usb: xhci: create one unified function to calculate TRB TD remainderChunfeng Yun2020-10-011-55/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xhci versions 1.0 and later report the untransferred data remaining in a TD a bit differently than older hosts. We used to have separate functions for these, and needed to check host version before calling the right function. Now Mediatek host has an additional quirk on how it uses the TD Size field for remaining data. To prevent yet another function for calculating remainder we instead want to make one quirk friendly unified function. Porting from the Linux: c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.") 124c39371114("xhci: use boolean to indicate last trb in td remainder calculation") Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | usb: xhci: add a member hci_version in xhci_ctrl structChunfeng Yun2020-10-012-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a member to save xHCI version, it's used some times. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | Revert "net: smc911x: Automatically Update ethaddr with MAC"Tom Rini2020-10-011-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon further discussion on the mailing list, we should not get in the situation where the generic code path to set ethaddr/etc correctly does not work. Revert this until someone can further debug the smc911x driver regarding this issue. This reverts commit 387cbf096e443705fa66776027273ed257ec6ca3. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | Merge branch 'next' of git://git.denx.de/u-boot-sh into nextTom Rini2020-10-012-12/+10
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| | * | net: ravb: Remove writeext function callBiju Das2020-09-261-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The micrel phy driver is already configuring this values from device tree. So remove the redundant phy configuration call from this driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| | * | pinctrl: renesas: Fix PINCTRL_PFC_R8A774A1 help descriptionBiju Das2020-09-261-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R8A774A1 is part of Renesas RZ/G2 series and not R-Car, reflect the same for PINCTRL_PFC_R8A774A1 help description Alongside, sort the PINCTRL_PFC_R8A774A1 config option as per increasing number of the SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | Merge branch '2020-09-30-assorted-network-improvements' into nextTom Rini2020-10-017-28/+300
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | - Generic UDP framework - TFTP fixes - dwc_eth_qos, smc911x, smc911x and mscc phy fixes
| | * | | net: dwc_eth_qos: Convert to use APIs which support live DTPatrick Delaunay2020-09-301-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| | * | | phy: add support for stingray PAXB PHY controllerSrinath Mannam2020-09-303-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for stingray PAXB PHY controller driver. This driver supports maximum 8 PAXB phys using pipemux data. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | | net: smc911x: Automatically Update ethaddr with MACAdam Ford2020-09-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ethernet controller can read the MAC from EEPROM and display it, but if ethaddr is not set, the ethernet is still unavailable. This patch checks will automatically set the MAC address if it has not already been set. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | | net: ftgmac100: Add support for board specific PHY interface addressThirupathaiah Annapureddy2020-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ftgmac100 driver is using hard-coded PHY interface address of zero. Each board can have different PHY interface address (phy_addr). This commit modifies the driver to make use of board specific address by leveraging CONFIG_PHY_ADDR. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| | * | | net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xxHeiko Stuebner2020-09-301-24/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel does set the clock delays to - 0.2 ns (their default, and lowest, hardware value) if delays should not be enabled - 2.0 ns (which causes the data to be sampled at exactly half way between clock transitions at 1000 Mbps) if delays should be enabled depending on the interface mode See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523 So instead of using arbitrary delay values like now, mimic this behaviour. The behaviour is the same for all of vsc8530/8531/8540/8541 so move that to a shared function while at it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| | * | | net: phy: mscc: make clock-output configurable on vsc85xxHeiko Stuebner2020-09-301-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vsc8530/8531/8540/8541 phys have a configurable clock output that can emit 25, 50 and 125 MHz rates, which in turn may be needed for stable network connections. This follows a similar change introduced into the Linux kernel at https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | | | firmware: smci: sandbox test for SCMI reset controllersEtienne Carriere2020-09-302-6/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tests for SCMI reset controllers. A test device driver sandbox-scmi_devices.c is used to get reset resources, allowing further resets manipulation. Change sandbox-smci_agent to emulate 1 reset controller exposed through an agent. Add DM test scmi_resets to test this reset controller. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | reset: add reset controller driver for SCMI agentsEtienne Carriere2020-09-304-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a reset controller driver for SCMI agent devices. When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent binds a reset controller device for each SCMI reset domain protocol devices enabled in the FDT. SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Reset Domain protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | firmware: scmi: sandbox test for SCMI clocksEtienne Carriere2020-09-303-5/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tests for SCMI clocks. A test device driver sandbox-scmi_devices.c is used to get clock resources, allowing further clock manipulation. Change sandbox-smci_agent to emulate 3 clocks exposed through 2 agents. Add DM test scmi_clocks to test these 3 clocks. Update DM test sandbox_scmi_agent with load/remove test sequences factorized by {load|remove}_sandbox_scmi_test_devices() helper functions. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | clk: add clock driver for SCMI agentsEtienne Carriere2020-09-304-3/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a clock driver for SCMI agent devices. When SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a clock device for each SCMI clock protocol devices enabled in the FDT. SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Clock protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Lukasz Majewski <lukma@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | firmware: scmi: support Arm SMCCC transportEtienne Carriere2020-09-303-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change implements a SMCCC transport for SCMI exchanges. This implementation follows the Linux kernel as references implementation for SCMI message processing, using the SMT format for communication channel meta-data. Use of SMCCC transport in SCMI FDT bindings are defined in the Linux kernel DT bindings since v5.8. SMCCC with SMT is implemented in OP-TEE from tag 3.9.0 [2]. Links: [2] https://github.com/OP-TEE/optee_os/commit/a58c4d706d23 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | firmware: scmi: mailbox/smt agent deviceEtienne Carriere2020-09-305-2/+333
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change implements a mailbox transport using SMT format for SCMI exchanges. This implementation follows the Linux kernel and SCP-firmware [1] as references implementation for SCMI message processing using SMT format for communication channel meta-data. Use of mailboxes in SCMI FDT bindings are defined in the Linux kernel DT bindings since v4.17. Links: [1] https://github.com/ARM-software/SCP-firmware Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | firmware: add SCMI agent uclassEtienne Carriere2020-09-306-0/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces SCMI agent uclass to interact with a firmware using the SCMI protocols [1]. SCMI agent uclass currently supports a single method to request processing of the SCMI message by an identified server. A SCMI message is made of a byte payload associated to a protocol ID and a message ID, all defined by the SCMI specification [1]. On return from process_msg() method, the caller gets the service response. SCMI agent uclass defines a post bind generic sequence for all devices. The sequence binds all the SCMI protocols listed in the FDT for that SCMI agent device. Currently none, but later change will introduce protocols. This change implements a simple sandbox device for the SCMI agent uclass. The sandbox nicely answers SCMI_NOT_SUPPORTED to SCMI messages. To prepare for further test support, the sandbox exposes a architecture function for test application to read the sandbox emulated devices state. Currently supports 2 SCMI agents, identified by an ID in the FDT device name. The simplistic DM test does nothing yet. SCMI agent uclass is designed for platforms that embed a SCMI server in a firmware hosted somewhere, for example in a companion co-processor or in the secure world of the executing processor. SCMI protocols allow an SCMI agent to discover and access external resources as clock, reset controllers and more. SCMI agent and server communicate following the SCMI specification [1]. This SCMI agent implementation complies with the DT bindings defined in the Linux kernel source tree regarding SCMI agent description since v5.8. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: Add support for regmap fieldsJean-Jacques Hiblot2020-09-301-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A regmap field is an abstraction available in Linux. It provides to access bitfields in a regmap without having to worry about shifts and masks. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
| * | | | regmap: Allow devices to specify regmap range start and size in configPratyush Yadav2020-09-301-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices need to calculate the regmap base address at runtime. This makes it impossible to use device tree to get the regmap base. Instead, allow devices to specify it in the regmap config. This will create a regmap with a single range that corresponds to the start and size given by the driver. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: Add regmap_init_mem_range()Pratyush Yadav2020-09-301-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now, the base of a regmap can only be obtained from the device tree. This makes it impossible for devices which calculate the base at runtime to use a regmap. An example of such a device is the Cadence Sierra PHY. Allow creating a regmap with one range whose start and size can be specified by the driver based on calculations at runtime. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: Allow left shifting register offset before accessPratyush Yadav2020-09-301-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drivers can configure it to adjust the final read/write location. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: Allow specifying read/write widthPratyush Yadav2020-09-301-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now, regmap_read() and regmap_write() read/write a 32-bit value only. To write other lengths, regmap_raw_read() and regmap_raw_write() need to be used. This means that any driver ported from Linux that relies on regmap_{read,write}() to know the size already has to be updated at each callsite. This makes the port harder to maintain. So, allow specifying the read/write width to make it easier to port the drivers, since now the only change needed is when initializing the regmap. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: zero out the regmap on allocationPratyush Yadav2020-09-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some fields will be introduced in the regmap structure that should be set to 0 by default. So, once we allocate a regmap, make sure it is zeroed out to avoid unexpected defaults for those values. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | regmap: Add devm_regmap_init()Jean-Jacques Hiblot2020-09-301-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of new linux drivers are using managed-API to allocate resources. To ease porting drivers from linux to U-Boot, introduce devm_regmap_init() as a managed API to get a regmap from the device tree. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
| * | | | drivers: gpio: Add a managed API to get a GPIO from the device-treeJean-Jacques Hiblot2020-09-301-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add managed functions to get a gpio from the devce-tree, based on a property name (minus the '-gpios' suffix) and optionally an index. When the device is unbound, the GPIO is automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
| * | | | test: reset: Add tests for the managed APIJean-Jacques Hiblot2020-09-302-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tests are basically the same as for the regular API. Except that the reset are initialized using the managed API, and no freed manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
| * | | | drivers: reset: Add a managed API to get reset controllers from the DTJean-Jacques Hiblot2020-09-301-4/+114
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add managed functions to get a reset_ctl from the device-tree, based on a name or an index. Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl) from the device-tree. When the device is unbound, the reset controllers are automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
| * | | Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini2020-09-307-38/+100
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next - Disable CMD_IRQ for RISC-V. - Update sipeed/maix doc - Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API. - Cleans up RISC-V timer drivers and converts them to DM. - Correctly handle IPIs already pending upon prior stage bootloader (on the K210)
| | * | | riscv: clk: Add CLINT clock to kendryte clock driverSean Anderson2020-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| | * | | timer: Add a test for timer_timebase_fallbackSean Anderson2020-09-302-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To test this function, sandbox CPU must set cpu_platdata.timebase_freq on bind. It also needs to expose a method to set the current cpu. I also make some most members of cpu_sandbox_ops static. On the timer side, the device tree property sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | timer: Add helper for drivers using timebase fallbackSean Anderson2020-09-301-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is designed to be used when a timer used to be initialized by the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In such a case, the timer may prefer to use the clocks and clock-frequency properties, but should be able to fall back on using the cpu's timebase-frequency. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
| | * | | riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-302-21/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
| | * | | ram: sifive: Remove regmap dependencyBin Meng2020-09-301-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usage of regmap API in the SiFive RAM driver is not correct. The reg address should be obtained via dev_read_addr_index() API. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| | * | | ram: sifive: Check return value on clk_enable()Bin Meng2020-09-301-0/+5
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | The return value should be checked otherwise it's useless to assign the return value to 'ret'. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * | | video: stm32: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no member `dev` in dw_mipi_dsi, but there is one in mipi_dsi_host, so use that. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: musb-new: sunxi: Fix not calling dev_err with a deviceSean Anderson2020-09-301-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver does not use DM, so we need to use a struct device instead of a struct udevice. Not ideal, but it'll have to do for now. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: dwc3: Don't include asm-generic/io.hSean Anderson2020-09-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can conflict with asm/io.h on some archs, and it isn't needed to build dwc3-generic.c Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: dwc3: ti: Fix not calling dev_err with a deviceSean Anderson2020-09-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver does not use DM, so use log_xxx instead. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: dwc3: Fix not calling dev_xxx with a deviceSean Anderson2020-09-303-18/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This logs with the device from struct dwc3. Some files also need to include dm.h so fields in udevice can be accessed. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: dwc2: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-16/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a dev argument to some functions so dev_xxx always has a device to log with. In one instance we must use use a different log function when we are compiled without DM_USB. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: cdns3: Fix not calling dev_xxx with a deviceSean Anderson2020-09-302-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ep0.c also need to include dm.h so dev_xxx can access udevice fields. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | sysreset: ti: Fix not calling dev_err with a deviceSean Anderson2020-09-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The rst variable doesn't exist. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | spi: zynqmp_gqspi: Fix not calling dev_err with a deviceSean Anderson2020-09-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use `bus` instead of `dev`. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | spi: sunxi: Fix not calling dev_err with a deviceSean Anderson2020-09-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use `bus` and not `dev`. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | soc: qualcomm: Fix not calling dev_err with a deviceSean Anderson2020-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the indirection. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
generated by cgit (git 2.34.1) at 2025-09-30 21:29:53 +0000