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* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-1435-6/+14182
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
| * | | spi: mvebu_a3700_spi: add support for cs-gpiosGeorge Hilliard2020-10-141-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree has a way to specify GPIO lines as chip selects. From the binding docs: So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : &gpio1 0 0 cs1 : native cs2 : &gpio1 1 0 cs3 : &gpio1 2 0 Add support for this, while retaining backward-compatibility with existing device trees; the driver will preserve existing behavior if a cs-gpios list is not given, or if a particular line is specified as <0> (native). This implementation is inspired by similar implementations in neighboring drivers for other platforms: atmega, mxc, etc. Signed-off-by: George Hilliard <ghilliar@amazon.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | net: Add NIC controller driver for OcteonTX2Suneel Garapati2020-10-1416-0/+4493
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | | net: Add NIC controller driver for OcteonTXSuneel Garapati2020-10-1414-0/+6656
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | | mtd: nand: Add NAND controller driver for OcteonTXSuneel Garapati2020-10-146-0/+2998
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | net: e1000: add defaults for i210 TX/RX PBSIZEChristian Gmeiner2020-10-142-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the defaults on probe for the packet buffer size registers for the i210. The TX/RX PBSIZE register of the i210 resets to its default value only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5 chapter 8.3 'Internal Packet Buffer Size Registers'. If something (another driver, another OS, etc.) modifies this register from its default value, the e1000 driver doesn't function correctly. It detects a hang of the transmitter and continuously resets the adapter. Here we set this value to its default when resetting the i210 to resolve this issue. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* | | | treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak2020-10-143-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | mmc: remove duplicate mmc_get_env_dev() implementationsDavid Woodhouse2020-10-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since it's so trivial I could just about tolerate this when there were only two copies of it. But now there are about to be three. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* | | | drivers: gpio: keep output value for input on sandboxHeinrich Schuchardt2020-10-141-1/+9
|/ / / | | | | | | | | | | | | | | | | | | | | | For testing purposes keep the output value when switching to input. This allows us to manipulate the input value via the gpio command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* | | Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini2020-10-128-33/+118
|\ \ \
| * | | arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang2020-10-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-094-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang2020-10-093-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | clk: agilex: Additional membus writes for HPS PLLChee Hong Ang2020-10-091-16/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang2020-10-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | | clk: agilex: Add clock enable supportLey Foon Tan2020-10-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | | clk: agilex: Add NAND clock supportLey Foon Tan2020-10-091-0/+3
| | |/ | |/| | | | | | | | | | | | | | | | Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | | Merge tag 'ti-v2021.01-rc1' of ↵Tom Rini2020-10-122-4/+11
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Minor cleanup on K3 env variables - Fix OSPI compatible for J721e - Drop unused property in omap-usb2-phy - Update Maintainer for am335x-guardian board.
| * | phy: omap-usb2-phy: Drop usage of "ti, dis-chg-det-quirk" DT propertyVignesh Raghavendra2020-10-121-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | "ti,dis-chg-det-quirk" property is not part of Linux kernel DT binding documentation. Therefore drop this and instead use soc_device_match() to distinguish b/w AM654 SR1.0 and SR2.0 devices similar to Linux kernel driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | dma: ti: k3-udma: Reset the channel during releaseVignesh Raghavendra2020-10-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Reset the channel completely during channel release in order to clear teardown bit before handing over to next user or jumping to Linux. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | | Kconfig: Move BOUNCE_BUFFER under driver optionsSimon Glass2020-10-091-0/+11
| | | | | | | | | | | | | | | | | | | | | This option does not belong at the top level. Move it under generic driver options. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | wdt: designware: fix timeout calculation due to expecting KHzJack Mitchell2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The timeout calculation is based on the clk being in KHz but the clk api returns the clk value in Hz. Convert this to KHz to calculate the correct timeout value. Signed-off-by: Jack Mitchell <ml@embed.me.uk>
* | | led: gpio: Default to using node name if label is absentSean Anderson2020-10-081-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | This more closely mirrors Linux's behaviour, and will make it easier to transition to using function+color in the future. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | gpio: dw: Return output value when direction is outSean Anderson2020-10-081-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | dm_gpio_ops.get_value can be called when the gpio is either input or output. The current dw code always returns the input value, which is invalid if the direction is set to out. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | | gpio: dw: Add a trailing underscore to generated nameSean Anderson2020-10-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, if there was no bank-name property, it was easy to have confusing gpio names like "gpio1@08", instead of "gpio1@0_8". This patch follows the example of the sifive gpio driver. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | gpio: dw: Fix warnings about casting int to pointerSean Anderson2020-10-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the type of gpio_dwabp_platdata.base from fdt_addr_t to a void pointer, since we pass it to readl. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | pinctrl: Add support for Kendryte K210 FPIOASean Anderson2020-10-083-0/+745
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | test: pinmux: Add test for pin muxingSean Anderson2020-10-081-48/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | pinctrl: Add pinmux property support to pinctrl-genericSean Anderson2020-10-081-30/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux property allows for smaller and more compact device trees, especially when there are many pins which need to be assigned individually. Instead of specifying an array of strings to be parsed as pins and a function property, the pinmux property contains an array of integers representing pinmux groups. A pinmux group consists of the pin identifier and mux settings represented as a single integer or an array of integers. Each individual pin controller driver specifies the exact format of a pinmux group. As specified in the Linux documentation, a pinmux group may be multiple integers long. However, no existing drivers use multi-integer pinmux groups, so I have chosen to omit this feature. This makes the implementation easier, since there is no need to allocate a buffer to do endian conversions. Support for the pinmux property is done differently than in Linux. As far as I can tell, inversion of control is used when implementing support for the pins and groups properties to avoid allocating. This results in some duplication of effort; every property in a config node is parsed once for each pin in that node. This is not such an overhead with pins and groups properties, since having multiple pins in one config node does not occur especially often. However, the semantics of the pinmux property make such a configuration much more appealing. A future patch could parse all config properties at once and store them in an array. This would make it easier to create drivers which do not function solely as callbacks from pinctrl-generic. This commit increases the size of the sandbox build by approximately 48 bytes. However, it also decreases the size of the K210 device tree by 2 KiB from the previous version of this series. The documentation has been updated from the last Linux commit before it was split off into yaml files. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ram: add ddr4 dual x8 configurationDylan Hung2020-10-083-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | the aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual x8 die or not. Or it may get the wrong size of the memory space. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | ram: move aspeed ram driver into drivers/ directoryDylan Hung2020-10-083-0/+443
| |/ |/| | | | | | | | | | | | | to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini2020-10-083-21/+11
|\ \ | | | | | | | | | | | | - Fix devicetree address determination seen on QEMU ARM64 - Use DMA for reads is available
| * | cfi_flash: Fix devicetree address determinationAndre Przywara2020-10-081-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cfi-flash driver uses an open-coded version of the generic algorithm to decode and translate multiple frames of a "reg" property. This starts off the wrong foot by using the address-cells and size-cells properties of *this* very node, and not of the parent. This somewhat happened to work back when we were using a wrong default size of 2, but broke about a year ago with commit 0ba41ce1b781 ("libfdt: return correct value if #size-cells property is not present"). Instead of fixing the reinvented wheel, just use the generic function that does all of this properly. This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding a wrong flash base address: DRAM: 1 GiB Flash: "Synchronous Abort" handler, esr 0x96000044 elr: 00000000000211dc lr : 00000000000211b0 (reloc) elr: 000000007ff5e1dc lr : 000000007ff5e1b0 x0 : 00000000000000f0 x1 : 000000007ff5e1d8 x2 : 000000007edfbc48 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 00000000000000f0 x6 : 000000007edfbc2c x7 : 0000000000000000 x8 : 000000007ffd8d70 x9 : 000000000000000c x10: 0400000000000003 x11: 0000000000000055 ^^^^^^^^^^^^^^^^ Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | mtd: cfi_mtd: Use DMA for readsVignesh Raghavendra2020-10-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When possible use DMA for reading from CFI flash, this provides upto 5x improvement in read performance with high speed CFI compliant flashes like HyperFlash. Code will gracefully fallback to CPU copy when DMA is unavailable. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | dma: Reduce error level when DMA channel type does not existVignesh Raghavendra2020-10-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Caller would need gracefully handle failures of dma_get_device(), therefore reduce pr_err() to pr_debug() when DMA device is not found. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | | Merge tag 'mips-pull-2020-10-07' of ↵Tom Rini2020-10-0712-3/+14597
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
| * | usb: xhci: octeon: Add DWC3 glue layer for OcteonStefan Roese2020-10-073-0/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the glue layer for the MIPS Octeon SoCs. It's ported mainly from the Linux code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addressesStefan Roese2020-10-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Octeon uses mapped addresses for virtual and physical memory. It's not that easy to calculate the resulting addresses here. So let's remove this BUG_ON() completely, as it's not really helpful. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()Stefan Roese2020-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * | ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)Aaron Williams2020-10-075-0/+435
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)Aaron Williams2020-10-071-0/+11030
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 2 includes the very complex Octeon 3 DDR4 configuration Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)Aaron Williams2020-10-071-0/+2728
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 1 adds the base U-Boot RAM driver, which will be instantiated by the DT based probing. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dmTom Rini2020-10-0611-19/+26
|\ \ \ | |/ / |/| | | | | | | | | | | bloblist enhancement for alignment Update ofnode/dev_read phandle function sandbox keyboard enhancements and fixes
| * | dm: add cells_count parameter in *_count_phandle_with_argsPatrick Delaunay2020-10-0611-19/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini2020-10-0611-222/+977
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
| * | pwm: Add driver for Amlogic Meson PWM controllerNeil Armstrong2020-10-053-0/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the driver for the PWM controller found in the Amlogic SoCs. This PWM is only a set of Gates, Dividers and Counters: PWM output is achieved by calculating a clock that permits calculating two periods (low and high). The counter then has to be set to switch after N cycles for the first half period. The hardware has no "polarity" setting. This driver reverses the period cycles (the low length is inverted with the high length) for PWM_POLARITY_INVERSED. Disabling the PWM stops the output immediately (without waiting for the current period to complete first). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | pinctrl: meson-axg: add missing GPIOA_18Neil Armstrong2020-10-051-0/+1
| | | | | | | | | | | | | | | | | | Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | pinctrl: meson-axg-pmx: fix gpio requestNeil Armstrong2020-10-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | The AXG pmx driver gpio request offset needs the pin base to have the correct pin number. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
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