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| * | net: sun8i-emac: Lower MDIO frequencyAndre Przywara2020-10-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i-emac: Make internal PHY handling more robustAndre Przywara2020-10-211-32/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Simplify and fix error handling for RXAndre Przywara2020-10-211-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix MAC soft resetAndre Przywara2020-10-211-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Fix overlong linesAndre Przywara2020-10-211-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Wrap and simplify cache maintenance operationsAndre Przywara2020-10-211-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Drop unneeded cache invalidation before sendingAndre Przywara2020-10-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Reduce cache maintenance on TX descriptor initAndre Przywara2020-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Improve cache maintenance on RX descriptor initAndre Przywara2020-10-211-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Name magic bits and simplify read-modify-write callsAndre Przywara2020-10-211-52/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Remove pointless wrapper functionsAndre Przywara2020-10-211-46/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Simplify mdio_read/mdio_write functionsAndre Przywara2020-10-211-41/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i_emac: Don't hand out TX descriptor too earlyAndre Przywara2020-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: sun8i-emac: Bail out on PHY errorAndre Przywara2020-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | rtc: move pcf8563 to KconfigHeiko Schocher2020-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | add Kconfig option for pcf8563 driver and run tools/moveconfig.py Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* | | mmc: mtk-sd: change some dev_err into dev_dbgFabien Parent2020-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | dev_err has been used for debugging and a few dev_err message are printed for normal code execution. Make them dev_dbg instead. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | serial: serial_xen: add DEBUG_UART supportAKASHI Takahiro2020-10-222-3/+31
| | | | | | | | | | | | | | | | | | | | | By using a hypervisor call, we can implement DEBUG_UART on xen. This will allow us to see messages even earlier than serial_init(). Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
* | | serial: serial_xen: print U-Boot banner and othersAKASHI Takahiro2020-10-221-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, DM_FLAG_PRE_RELOC is set only if !OF_CONTROL. It doesn't make sense for this para-virtualized driver. With this patch applied, you will be able to see early boot messages: U-Boot 2020.10-00001-ge442e71a6c52-dirty (Oct 15 2020 - 11:02:25 +0900) xenguest Xen virtual CPU Model: XENVM-4.15 DRAM: 128 MiB PVBLOCK: (XEN) gnttab_mark_dirty not implemented yet pvblock: 0 In: hypervisor Out: hypervisor Err: hypervisor xenguest# Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | cosmetic: reset: ast2500: Rename driver and configsChia-Wei, Wang2020-10-223-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Rename AST2500 reset driver from ast2500-reset.c to reset-ast2500.c 2. Rename AST2500 reset kconfig option from AST2500_RESET to RESET_AST2500 Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-222-51/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | clk: ccf: replace the get_rate helperDario Binacchi2020-10-221-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The 12d152620d commit fixed the get_rate helper because the set_parent one did not re-parent the clock device to the new parent. The 4d139f3838 commit allows you to remove this workaround by calling the clk_get_parent_rate routine. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | | ARM: mvebu: a38x: Fix comment typoNaoki Hayama2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | %s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp> Reviewed-by: Stefan Roese <sr@denx.de>
* | | mmc: Fix comment typoNaoki Hayama2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | %s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
* | | rng: Add Qualcomm MSM PRNG driverRobert Marko2020-10-223-0/+151
| | | | | | | | | | | | | | | | | | | | | Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | net: Add IPQ40xx MDIO driverRobert Marko2020-10-223-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | spi: Add Qualcomm QUP SPI controller driverRobert Marko2020-10-223-0/+814
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | timer: Return count from timer_ops.get_countSean Anderson2020-10-2221-86/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | No timer drivers return an error from get_count. Instead of possibly returning an error, just return the count directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | common: rename getc() to getchar()Heinrich Schuchardt2020-10-224-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandbox is built with the SDL2 library with invokes the X11 library which in turn calls getc(). But getc() in glibc is defined as int getc(FILE *) This does not match our definition. int getc(void) The sandbox crashes when called with parameter -l. Rename our library symbol getc() to getchar(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | tpm: cr50: Correct logging statementsSimon Glass2020-10-221-5/+5
| | | | | | | | | | | | | | | | | | | | | Fix up some logging statements in this file. Most of them should use log_debug(), apart from one error. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | i2c: designware: Use log_debug() for debuggingSimon Glass2020-10-221-2/+2
| | | | | | | | | | | | | | | | | | | | | We don't want the debug output to be visible in a normal boot. Silence it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de>
* | | syscon: Drop the logging in syscon_get_by_driver_data()Simon Glass2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be called when it is not known whether it will find anything. This results in confusing log messages if the device is not found. It is better for the caller to log the failure, if necessary. Drop the logging from this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini2020-10-223-17/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
| * | | arm: stm32: cleanup arch gpio.hPatrick Delaunay2020-10-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc2020-10-211-16/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc2020-10-211-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2020-10-208-28/+1059
|\ \ \ | | | | | | | | | | | | - Assorted R-Car Gen3 updates
| * | | pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9Lad Prabhakar2020-10-201-27/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar2020-10-203-0/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | clk: renesas: Add R8A774E1 clock tablesBiju Das2020-10-203-0/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | clk: renesas: Add R8A774B1 clock tablesBiju Das2020-10-203-0/+343
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das2020-10-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility stringBiju Das2020-10-201-1/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | | usb: gadget: Add bcdDevice for the MTU3 USB Gadget ControllerChunfeng Yun2020-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add an entry in usb_gadget_controller_number() for the MTU3 gadget controller. It is used to bind the USB Ethernet driver. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: add MediaTek USB3 DRD driverChunfeng Yun2020-10-2013-0/+4557
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: common: add define of usb_speed_string()Chunfeng Yun2020-10-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | There is only declaration of usb_speed_string(), but no definition, so add it to avoid build error when call it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: add USB_SPEED_SUPER_PLUSChunfeng Yun2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | Add enum USB_SPEED_SUPER_PLUS for USB3.1 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | usb: musb-new: Fix typo in caution messageNaoki Hayama2020-10-201-1/+1
| | | | | | | | | | | | | | | | | | %s/Occured/Occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
* | | usb: dwc2: Fix control OUT transfer issueChance.Yang2020-10-201-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In buffer DMA mode, gadget should re-configure EP 0 to received SETUP packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes) and EP 0 is in WAIT_FOR_SETUP state. Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT received from RxFifo and wriiten to the external memory. Signed-off-by: Chance.Yang <chance.yang@vatics.com>
* | | usb: xhci: avoid type conversion of void *Heinrich Schuchardt2020-10-201-12/+9
|/ / | | | | | | | | | | | | void * can be assigned to any pointer variable. Avoid unnecessary conversions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini2020-10-195-4/+654
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
generated by cgit (git 2.34.1) at 2025-09-28 17:56:56 +0000