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| * | sandbox: i2c: Move priv into a header fileSimon Glass2021-01-051-4/+1
| | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: serial: Move priv into a header fileSimon Glass2021-01-051-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | x86: pinctrl: Drop unlikely error messages from TPLSimon Glass2021-01-051-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | These errors are only really for development purposes. Drop them to reduce the size of TPL. The error numbers are still reported. This reduces the TPL binary size on coral by about 160 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: apl: Reduce size for TPLSimon Glass2021-01-054-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | test: Move some test drivers into their own fileSimon Glass2021-01-053-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present several test drivers are part of the test file itself. Some of these are useful for of-platdata tests. Separate them out so we can use them for other things also. A few adjustments are needed so this driver can build for sandbox_spl as well. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sysreset: Use a shorter error with SPLSimon Glass2021-01-051-4/+8
| | | | | | | | | | | | | | | | | | | | | Use a minimal error message to save space. Sort the header files while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: Drop post_bind() method when not neededSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | | | This is not used with of-platdata, so remove it in that case. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Rename the priv/plat membersSimon Glass2021-01-052-14/+14
| | | | | | | | | | | | | | | | | | | | | These are supposed to be private to driver model, not accessed by any code outside. Add a trailing underscore to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Use access methods for dev/uclass private dataSimon Glass2021-01-053-37/+45
| | | | | | | | | | | | | | | | | | | | | | | | Use these functions in the core code as much as possible. With this, there are only two places where each priv/plat pointer is accessed, one for read and one for write. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Use access methods for dev/uclass private dataSimon Glass2021-01-05103-244/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
| * | dm: core: Add functions to set priv/platSimon Glass2021-01-051-0/+30
| | | | | | | | | | | | | | | | | | | | | This should not normally be needed in drivers, but add accessors for the few cases that exist. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Add function to access uclass privSimon Glass2021-01-051-0/+10
| | | | | | | | | | | | | | | | | | | | | Add functions so this information is not accessed directly. This will be needed for of-platdata which stores it in a different place. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: apl: Drop support for !OF_PLATDATA_PARENTSimon Glass2021-01-052-17/+0
| | | | | | | | | | | | | | | | | | | | | This code was kept around after of-platdata started supporting parent devices. That feature seems stable now, so let's drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Only include simple-bus devicetree id when neededSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | | | This is not needed when of-platdata is in use. Update it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Use 'uclass_driver' for the uclass linker_listSimon Glass2021-01-052-4/+4
| | | | | | | | | | | | | | | | | | | | | At present the name 'uclass_driver' is used for the uclass linker list. This does not follow the convention of using the struct name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Support dm_dump_all() in SPLSimon Glass2021-01-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | At present the output from this function is hard to read in SPL, due to (intended) limitations in SPL's printf() function. Add an SPL version so it is clearer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | serial: Rename ns16550 functions to lower caseSimon Glass2021-01-052-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | serial: Update NS16550_t and struct NS16550Simon Glass2021-01-056-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-0552-223/+1195
|\ \ \ | |/ / |/| | | | | | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * | cosmetic: fix typo in drivers/usb/KconfigMarc Ferland2021-01-041-1/+1
| | | | | | | | | | | | | | | | | | This commit fixes a simple typo: sPL --> SPL. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
| * | nvme: Use only 32-bit accesses in nvme_writeq/nvme_readqStefan Agner2021-01-041-8/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There might be hardware configurations where 64-bit data accesses to NVMe registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit NVMe registers, similarly as it is done in Linux kernel. This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC based board, where the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. nvme_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail probing. This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq"). Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Cc: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
| * Merge tag 'u-boot-imx-20201227' of ↵Tom Rini2020-12-281-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2021.1 ---------------- CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680 - fixes for Variscite dart6ul - imx8mp : increase malloc area - fixes for bx50v3 - imx8m: HS400ES and UHS for EVK - imx8qm-rom7720: fix phy bind
| | * i2c: mxc_i2c: improve error message readabilityMarc Ferland2020-12-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use 0x%2lx to print the i2c bus base address in hexadecimal format instead of printing as an integer. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"Pali Rohár2020-12-281-3/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 828d32621686aec593076d16445d39b9b8d49c05. This change revers code which asserting PERST# signal when unloading driver. Driver's remove callback is still there as it is used for other functionality. Asserting PERST# signal prior booting kernel is causing that A3720 boards (Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and 4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900) and anymore. When PERST# signal is not asserted these cards are detected correctly. As this is regression for existing stable Linux kernel versions revert this problematic change in U-Boot. To make cards working with OpenWRT 4.14 kernel it is needed to disable link training prior booting kernel, which is already done in driver's remove callback. Described issue is in Linux kernel pci aardvark driver which is (hopefully) fixed in latest upstream versions. Latest upstream versions should be able to initialize PCIe bus and detects cards independently of the link training and PERST# signal state. So with this change, U-Boot on A3720 boards should be able to boot OpenWRT 4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini2020-12-188-136/+944
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| | * mtd: spi-nor-ids: add Micron MT25QL01G flashHongwei Zhang2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: ca_sflash: Add CAxxxx SPI Flash ControllerPengpeng Chen2020-12-183-0/+585
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Add mem_opsSean Anderson2020-12-181-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The designware ssi device has "broken" chip select behaviour [1], and needs specific manipulation to use the built-in chip select. The existing fix is to use an external GPIO for chip select, but typically the K210 has SPI3 directly connected to a flash chip with dedicated pins. This makes it impossible to use the spi_xfer function to use spi, since the CS is de-asserted in between calls. This patch adds an implementation of exec_op, which gives correct behaviour when reading/writing spi flash. This patch also rearranges the headers to conform to U-Boot style. [1] https://lkml.org/lkml/2015/12/23/132 Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Add support for multiple CTRLR0 layoutsSean Anderson2020-12-181-35/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/ Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Rearrange struct dw_spi_privSean Anderson2020-12-181-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This should reduce the size of the struct, and also groups more similar fields together. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Remove spi_enable_chipSean Anderson2020-12-181-11/+6
| | | | | | | | | | | | | | | | | | | | | This function does nothing but wrap dw_write. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Rename registers to match datasheetSean Anderson2020-12-181-9/+9
| | | | | | | | | | | | | | | | | | | | | A few registers had slightly different names from what is in the datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Use generic function to read reg addressSean Anderson2020-12-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Using an fdt-specific function causes problems when compiled with a live tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Rename "cs-gpio" to "cs-gpios"Sean Anderson2020-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This property is named differently than other SPI drivers with the same property, as well as the property as used in Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Convert calls to debug to dev_*Sean Anderson2020-12-181-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows different log levels to be enabled or disabled depending on the desired level of verbosity. In particular, it allows for general debug information to be printed while excluding more verbose logging which may interfere with timing. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Fix driving MOSI low while recievingSean Anderson2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The resting state of MOSI is high when nothing is driving it. If we drive it low while recieving, it looks like we are transmitting 0x00 instead of transmitting nothing. This can confuse slaves (like SD cards) which allow new commands to be sent over MOSI while they are returning data over MISO. The return of MOSI from 0 to 1 at the end of recieving a byte can look like a start bit and a transmission bit to an SD card. This will cause the card to become out-of-sync with the SPI device, as it thinks the device has already started transmitting two bytes of a new command. The mmc-spi driver will not detect the R1 response from the SD card, since it is sent too early, and offset by two bits. This patch fixes transfer errors when using SD cards with dw spi. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * mtd: spinand: enable erasing of bad mtd blocksMikhail Kshevetskiy2020-12-181-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot is able to erase bad mtd blocks on raw nand devices, but this is not true for spinand flashes. Lets enable this feature for spinand flashes as well. This is extemelly useful for flash testing. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru>
| | * mtd: spinand: Do not erase the block before writing a bad block markerFrieder Schrempf2020-12-181-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
| | * mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOBFrieder Schrempf2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
| | * mtd: spinand: Stop using spinand->oobbuf for buffering bad block markersFrieder Schrempf2020-12-181-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
| | * mtd: spi-nor-ids: Add SECT_4K to mx25l12805dRobert Marko2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx25l12805d datasheet it supports using 4K or 64K sectors. So lets add the SECT_4K to enable 4K sector usage. Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * mtd: spi-nor-ids: Add Winbond W25M512JW flash entryBiju Das2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25M512JW flash device description. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * mtd: spi-nor-ids: Add Winbond W25M512JV flash entryLad Prabhakar2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25M512JV flash device description. Linux already has the flash entry present. A snippet below: { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...}, Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: migrate trace to dev and log macro in spi uclassPatrick Delaunay2020-12-181-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define LOG_CATEGORY and change printf and pr_* to dev_ (when dev is available) or log_ macro. This patch adds the support of logging feature with log command (filtering, display of device name in trace) and allows to suppress traces via the syslog driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2020-12-163-7/+42
| |\ \ | | |/ | |/| | | | - r8152, xhci fixes
| | * eth/r8152: fix the aggregation issueHayes Wang2020-12-162-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for RTL8153B, it is necessary to notify the hardware of the changes of the aggregation settings. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
| | * eth/r8152: free previous memory if r8152_eth_probe failHayes Wang2020-12-161-2/+7
| | | | | | | | | | | | | | | | | | | | | The r8152_eth_probe() may allocate a memory for ss->dev_priv. It has to be freed if r8152_eth_probe() fails finally. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
| | * usb: xhci: fix lack of short packet event trb handlingRan Wang2020-12-161-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For bulk IN transfer, the codes will set ISP flag to request event TRB being generated by xHC for the case of short packet. So when encountering buffer-cross-64K-boundary (which we will divide payload and enqueuqe more than 1 transfer TRB), and the first TRB ends up with a short packet condition it will trigger an short packet code transfer event per that flag and cause more than 1 event TRB generated for this transfer. However, current codes will only handle the first transfer event TRB then mark current transfer completed, causing next transfer failure due to event TRB mis-match. Such issue has been observed on some Layerscape platforms (LS1028A, LS1088A, etc) with USB ethernet device. This patch adds a loop to make sure the event TRB for last transfer TRB has been handled in time. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: edison: Use dwc3-generic driver for Intel EdisonAndy Shevchenko2020-12-161-0/+1
| |/ | | | | | | | | | | | | | | | | Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * pinctrl: meson: fix bit manipulation of pin bias configurationNeil Armstrong2020-12-141-2/+2
| | | | | | | | | | | | | | | | | | This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument. Fixes: c4c726c26b ("pinctrl: meson: add pinconf support") Reported-by: Anton Arapov <arapov@gmail.com> Reported-by: Otto Meier <gf435@gmx.net> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
generated by cgit (git 2.34.1) at 2024-10-03 00:26:05 +0000