summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* image: Adjust the workings of fit_check_format()Simon Glass2021-02-153-5/+5
| | | | | | | | | | | | | | | | | At present this function does not accept a size for the FIT. This means that it must be read from the FIT itself, introducing potential security risk. Update the function to include a size parameter, which can be invalid, in which case fit_check_format() calculates it. For now no callers pass the size, but this can be updated later. Also adjust the return value to an error code so that all the different types of problems can be distinguished by the user. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Bruce Monroe <bruce.monroe@intel.com> Reported-by: Arie Haenel <arie.haenel@intel.com> Reported-by: Julien Lenoir <julien.lenoir@intel.com>
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-15351-4/+354
|\ | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-02351-4/+354
| | | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | sh: Remove sh7757lcr boardTom Rini2021-02-151-4/+0
| | | | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. As this is the last SH4A board, remove that support as well. Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | sh: Remove r7780mp boardTom Rini2021-02-153-211/+0
| | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. Patch-cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Patch-cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: Remove ls2080a_simu boardTom Rini2021-02-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it. Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm: Remove mx35pdk boardTom Rini2021-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | Merge tag 'u-boot-atmel-fixes-2021.04-a' of ↵Tom Rini2021-02-121-8/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel fixes for 2021.04 cycle: This small PR includes just two fixes but very important: one revert in the clk subsystem which fixes the boot on many old boards (sama5d2_xplained, sama5d4_xplained), which currently crash at boot; and one small fix related to debug serial on sama7g5ek board.
| * | clk: at91: compat: partially revert "dm: Remove uses of device_bind_offset()"Eugen Hristev2021-02-111-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert changes in at91 compat.c that cause u-boot to fail booting on sama5d4_xplained and sama5d2_xplained Log below: <debug_uart> No serial driver found Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Fixes: a2703ce10c ("dm: Remove uses of device_bind_offset()") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | usb: dwc2: change compatible st,stm32mp1-hsotg to st,stm32mp15-hsotgPatrick Delaunay2021-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel v5.7-rc1 introduced the compatible "st,stm32mp15-hsotg". See Linux kernel commit d49850110434 ("dt-bindings: usb: dwc2: add support for STM32MP15 SoCs USB OTG HS and FS") This patch updates the supported compatible in DWC2 driver, removes the add-on done in U-Boot dtsi and keeps the compatible defined in SOC dtsi arch/arm/dts/stm32mp151.dtsi: usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; ... }; Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | usb: xhci: Fix compare to use physical addresses in xhci_bulk_tx()Stefan Roese2021-02-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing with v2021.01 on MIPS Octeon has shown, that the latest patch for the "short packet event trb handling" did introduce a bug on platforms with virtual address != physical address. This patch fixes this issue by using the correct address types in the compare (both physical in this case). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Ran Wang <ran.wang_1@nxp.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Cc: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com>
* | | usb: xhci-pci: Check for errors from dm_pci_map_bar()Pali Rohár2021-02-101-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dm_pci_map_bar() may fail and returns NULL. Check this to prevent dereferencing a NULL pointer. In xhci-pci this may happen when board does not enable CONFIG_PCI_PNP and PCI_BASE_ADDRESS_0 contains unconfigured zero address. Signed-off-by: Pali Rohár <pali@kernel.org>
* | | usb: xhci-mtk: support option to disable portsChunfeng Yun2021-02-101-3/+20
|/ / | | | | | | | | | | | | | | | | | | | | Add support to disable specific ports, it's useful for some scenarios: 1. usb3 PHY is shared whith PCIe or SATA, the corresponding usb3 port can be disabled; 2. some usb2 or usb3 ports are not used on special platforms, they should be disabled to save power. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | Merge tag 'u-boot-amlogic-20210210' of ↵Tom Rini2021-02-106-0/+824
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Add configuration helpers for MIPI D-PHY - generic-phy: add configure op - Add Amlogic AXG MIPI D-PHY driver & MIPI PCIe Analog PHY driver - odroid: add runtime detection of the N2/N2+/C4/HC4 variants
| * | phy: Add Amlogic AXG MIPI PCIe Analog PHY driverNeil Armstrong2021-02-103-0/+243
| | | | | | | | | | | | | | | | | | | | | | | | The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission and Analog part of the PCIe lines. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | phy: Add Amlogic AXG MIPI D-PHY driverNeil Armstrong2021-02-103-0/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. This D-PHY depends on a separate analog PHY. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | generic-phy: add configure opNeil Armstrong2021-02-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PHY configure op callback to the generic PHY uclass to permit configuring the PHY. It's useful for MIPI DSI PHYs to setup the link timings. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | phy: dphy: Add configuration helpersNeil Armstrong2021-02-103-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | clk: stm32mp1: add support of I2C6_KPatrick Delaunay2021-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR = I2C6EN: I2C6 peripheral clocks enable. This patch allows customer to use I2C6 in SPL or in U-Boot as other I2C instance, already support in clk driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | | pinctrl: stm32: bind only the enabled GPIO subnodePatrick Delaunay2021-02-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | | pinctrl: stm32: correct management pin display of OTYPEPatrick Delaunay2021-02-091-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | | pinctrl: stmfx: Use PINNAME_SIZE for pin's name sizePatrice Chotard2021-02-091-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | Instead of redefining a pin's name size, use PINNAME_SIZE defined in include/dm/pinctrl.h Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | pinctrl: stmfx: Fix pin configuration issuePatrice Chotard2021-02-091-4/+4
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin-controller pin's name must be equal to pin's name used in device tree with "pins" DT property. Issue detected on stm32mp157c-ev1 board with goodix touchscreen. In DT, the goodix's pin is declared in DT with the node: goodix_pins: goodix { pins = "gpio14"; bias-pull-down; }; Whereas in stmfx pin-controller driver, pin's name are equal to "stmfx_gpioxx" where xx is the pin number. This lead to not configure stmfx's pins at probe because pins is identified by its name (see pinctrl_pin_name_to_selector() in pinctrl-generic.c) and stmfx pin "gpio14" can't be found. To fix this issue, come back to the original stmfx pin's name. Revert "pinctrl: stmfx: update pin name" This reverts commit 38d30cdcd65c73eeefac5efa328ad444a53b77dd. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2021-02-082-39/+31
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Espressobin: Set default env values at runtime (Pali) - Espressobin: Set the maximum slave SPI speed to 40MHz (Pali) - theadorable: PCIe test code enhancement and early deemphasis enabling (Stefan) - pci_mvebu: Disable config access to PCI host bridge ports (Stefan) - mv_sdhci: parse device-tree entry (Baruch)
| * | mmc: mv_sdhci: parse device-tree entryBaruch Siach2021-02-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call mmc_of_parse() so that generic DT properties like 'non-removable' are taken into account. This fixes boot on Clearfog with eMMC on SOM that requires the non-removable property. Reported-by: Thorsten Spille <thorsten_spille@netcor.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
| * | pci: pci_mvebu: Disable config access to PCI host bridge portsStefan Roese2021-02-081-39/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the PCI config routines in the Armada XP / 38x driver to not allow access to the PCIe root ports. While updating the Armada XP based theadorable to the latest mainline and testing it with the DM PCI driver I noticed, that the PCI root bridge was being configured incorrectly. Resulting in the PCIe Intel WiFi was not working correctly in Linux. With this patch applied, all PCIe devices work without any issues in Linux again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2021-02-088-84/+89
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape: Enable gpio Bug fixes & updates related to dspi, qspi, pciep, SVR mask, stream-id, env variables, mdio for LAyerscape Platforms Add SATA, network variant 1, 2 support on sl28 powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile Bug fixes and updates for keymile, Kontron
| * | | gpio: mpc8xxx_gpio: Fix for litte endianBiwen Li2021-02-081-39/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: kconfig: layerscape: Change LX2162A PCIe node compatible stringHou Zhiqiang2021-02-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: Remove the shadow SVR definitionsHou Zhiqiang2021-02-081-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | spi: fsl_qspi: apply the same settings for LS1088 as LS208xMathew McBride2021-02-081-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | spi: fsl_qspi: Ensure width is respected in spi-mem operationsMathew McBride2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: eqos: Reduce the MDIO wait timeYe Li2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: memac_phy: add a timeout to MDIO operationsIoana Ciornei2021-02-081-18/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | mtd: spi-nor: add unlock all config optionMichael Walle2021-02-082-4/+15
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an explicit configuration option to disable default "unlock all" of any flash chip which supports locking. It doesn't make sense to automatically unprotect the entire flash on each u-boot startup if the block protection bits are actually used. Traditionally, the unlock was there to be able to write to flash devices which powered-up with the block protection bits set. Over time this feature creeped into all flash devices which support locking. For a more detailed description and discussion see: https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/ Keep things simple in u-boot and just provide a configration option to disable this behavior which can be set per board. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | fastboot: reinit partition after storing GPT or MBRRoman Stratiienko2021-02-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case MMC has MBR system and fastboot writes GPT, MMC is still recognized as MBR. Invoke part_init() to purge cached data and update information about partition table type. Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
* | | fastboot: add command to select the eMMC boot configurationPatrick Delaunay2021-02-072-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command oem bootbus which executes the command ``mmc bootbus <id> <arg>`` on the current fastboot mmc device (<i> = CONFIG_FASTBOOT_FLASH_MMC_DEV) to set the eMMC boot configuration on first update, with <arg> = boot_bus_width reset_boot_bus_width boot_mode $> fastboot oem bootbus:<boot_bus_width> <reset_boot_bus_width> <boot_mode> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | fastboot: add command to select the default emmc hwpart for bootPatrick Delaunay2021-02-072-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add fastboot command oem partconf which executes the command ``mmc partconf <id> <arg> 0`` on the current <id> mmc device to configure the eMMC boot partition with <arg>: boot_ack boot_partition, so the command is: $> fastboot oem partconf:<boot_ack> <boot_partition> The partition_access argument is forced to 0 (userdata) Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [lukma - Kconfig adjustments after merging this patch]
* | | fastboot: mmc: extend flash/erase for both emmc hwpart 1 and 2Patrick Delaunay2021-02-072-24/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code and the configs for eMMC boot and userdata partitions acces - FASTBOOT_MMC_BOOT_SUPPORT: boot partition 1 and 2 (erase/write) - FASTBOOT_MMC_BOOT1_NAME: boot partition 1, default name="mmc0boot0" - FASTBOOT_MMC_BOOT2_NAME: boot partition 2, default name="mmc0boot1" This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | fastboot: mmc: Add CONFIG_FASTBOOT_MMC_USER_SUPPORTPatrick Delaunay2021-02-072-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split userdata and boot partition support for eMMC update and correct the description (update is supported). The new configuration CONFIG_FASTBOOT_MMC_USER_SUPPORT allows to activate support of userdata partition update, based on target name=CONFIG_FASTBOOT_MMC_USER_NAME This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | fastboot: Implement generic fastboot_set_reboot_flagRoman Kovalivskyi2021-02-071-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible to implement fastboot_set_reboot_flag in a generic way if BCB commands are turned on for a target. Using bcb_set_reboot_reason allows to do this by simply passing string with correct reboot reason that should be handled during next boot process. If BCB are turned off, then bcb_set_reboot_reason would simply return error, so it won't introduce any new behaviour for such targets. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
* | | Revert "fastboot: Add default fastboot_set_reboot_flag implementation"Roman Kovalivskyi2021-02-073-56/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0ebf9842e56c5b8cb7cb1f990bb452cc14af6225. Current generic implementation of fastboot_set_reboot_flag is somewhat messy and requires some additional configuration option to be enabled besides CMD_BCB, so it reverts that implementtion in order to bring a new cleaner one. Next commit introduces new generic implementation of fastboot_set_reboot_flag. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
* | | dfu: dfu_sf: use correct print codeHeinrich Schuchardt2021-02-071-1/+1
|/ / | | | | | | | | | | For printing unsigned int %u has to be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'ti-v2021.04-rc2' of ↵Tom Rini2021-02-054-112/+376
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Sync DTS from Linux kernel for all K3 platforms - Add MMC higher speed nodes for AM65x, J721e, J7200 - Convert Nokia RX-51 to use CONFIG_DM_MMC - Minor fixes for LEGO MINDSTORMS
| * | mmc: am654_sdhci: Use sdhci_set_control_reg()Faiz Abbas2021-02-041-16/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic sdhci_set_control_reg() instead of duplicating in platform driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modesFaiz Abbas2021-02-042-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch. To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes. Use the sdhci writeb callback to implement this condition. [1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: am654_sdhci: Add support for software tuningFaiz Abbas2021-02-041-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: am654_sdhci: Add support for writing to clkbuf_selFaiz Abbas2021-02-041-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for writing new clock buffer select property for both the am654x and j721e 4 bit IPs Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: am654_sdhci: Add support for input tap delayFaiz Abbas2021-02-041-80/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. Therefore, move all dll configurations to their own functions and gate it with 50 MHz speed and a minimum mode. If both these conditions are not satisfied then configure delay chain modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: am654_sdhci: Add support for AM65x SR2.0Faiz Abbas2021-02-041-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the platform data and do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
generated by cgit (git 2.34.1) at 2024-09-24 13:06:05 +0000