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| * | | dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-0527-39/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Rename U_BOOT_DEVICE() to U_BOOT_DRVINFO()Simon Glass2021-01-0513-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add logging when lists_bind_fdt() failsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to see the error code when this fails. Add logging for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Allow the uclass list to moveSimon Glass2021-01-053-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the uclass list head is in global_data. This is convenient but with the new of-platdata we need the list head to be declared by the generated code. Change this over to be a pointer. Provide a 'static' version in global_data to retain the current behaviour. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Split out scanning code to dm_scan()Simon Glass2021-01-051-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code related to scanning for devices to bind, into a new function. This will make it easier to skip this step with the new of-platdata improvements. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Access device ofnode through functionsSimon Glass2021-01-0543-70/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass2021-01-0512-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | dm: core: Rename dev_has_of_node() to dev_has_ofnode()Simon Glass2021-01-054-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We use 'ofnode' rather than 'of_node' in U-Boot. Rename this function to fit. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Access device flags through functionsSimon Glass2021-01-058-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At present flags are stored as part of the device. In preparation for storing them separately, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Rename sqq to seq_Simon Glass2021-01-054-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the sequence-numbering migration is complete, rename this member back to seq_, adding an underscore to indicate it is internal to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | dm: core: Split out alloc code into a new functionSimon Glass2021-01-051-37/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new function to handle the allocation of private/platform data for a device. This will make it easier to skip this feature when using the new of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: sysreset: Move priv/plat structs to headersSimon Glass2021-01-051-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them and add the dtd struct too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | dm: core: Move priv/plat structs for simple_bus to headersSimon Glass2021-01-051-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | spi: Tweak a few strange SPI NOR features for of-platdataSimon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The #define of one struct to another has been around for a while. It confuses dtoc and makes it think that struct spi_flash does not exist. Make a few changes to improve things while we wait for migration to be completed: - Move the 'struct spi_flash' to column 1 so dtoc scans it - Remove the #define when compiling dt-platdata.c - Update the strange mtd_get/set_of_node() functions - Use struct spi_nor in the drivers, so dtoc sees the correct struct Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | spi: Tidy up get/set of device nodeSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is a bit odd in that it only reads and updates the livetree version of the device ofnode. This means it won't work with flattree. Update the code to work as it was presumably intended. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: spl: Move priv/plat structs to headersSimon Glass2021-01-052-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Move priv/plat structs to headersSimon Glass2021-01-051-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Add a compatible string for spltestSimon Glass2021-01-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this driver does not have a compatible string. For it to be used with the coming of-platadata, it must have one. Update it accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: i2c: Move priv into a header fileSimon Glass2021-01-051-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: serial: Move priv into a header fileSimon Glass2021-01-051-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | x86: pinctrl: Drop unlikely error messages from TPLSimon Glass2021-01-051-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These errors are only really for development purposes. Drop them to reduce the size of TPL. The error numbers are still reported. This reduces the TPL binary size on coral by about 160 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Reduce size for TPLSimon Glass2021-01-054-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | test: Move some test drivers into their own fileSimon Glass2021-01-053-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present several test drivers are part of the test file itself. Some of these are useful for of-platdata tests. Separate them out so we can use them for other things also. A few adjustments are needed so this driver can build for sandbox_spl as well. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sysreset: Use a shorter error with SPLSimon Glass2021-01-051-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a minimal error message to save space. Sort the header files while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | pinctrl: Drop post_bind() method when not neededSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is not used with of-platdata, so remove it in that case. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Rename the priv/plat membersSimon Glass2021-01-052-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These are supposed to be private to driver model, not accessed by any code outside. Add a trailing underscore to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Use access methods for dev/uclass private dataSimon Glass2021-01-053-37/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use these functions in the core code as much as possible. With this, there are only two places where each priv/plat pointer is accessed, one for read and one for write. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Use access methods for dev/uclass private dataSimon Glass2021-01-05103-244/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
| * | | dm: core: Add functions to set priv/platSimon Glass2021-01-051-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This should not normally be needed in drivers, but add accessors for the few cases that exist. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add function to access uclass privSimon Glass2021-01-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions so this information is not accessed directly. This will be needed for of-platdata which stores it in a different place. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: apl: Drop support for !OF_PLATDATA_PARENTSimon Glass2021-01-052-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This code was kept around after of-platdata started supporting parent devices. That feature seems stable now, so let's drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Only include simple-bus devicetree id when neededSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is not needed when of-platdata is in use. Update it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Use 'uclass_driver' for the uclass linker_listSimon Glass2021-01-052-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the name 'uclass_driver' is used for the uclass linker list. This does not follow the convention of using the struct name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Support dm_dump_all() in SPLSimon Glass2021-01-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the output from this function is hard to read in SPL, due to (intended) limitations in SPL's printf() function. Add an SPL version so it is clearer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | serial: Rename ns16550 functions to lower caseSimon Glass2021-01-052-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | serial: Update NS16550_t and struct NS16550Simon Glass2021-01-056-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | | | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-0552-223/+1195
|\ \ \ \ | |/ / / |/| | / | | |/ | |/| | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * | cosmetic: fix typo in drivers/usb/KconfigMarc Ferland2021-01-041-1/+1
| | | | | | | | | | | | | | | | | | This commit fixes a simple typo: sPL --> SPL. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
| * | nvme: Use only 32-bit accesses in nvme_writeq/nvme_readqStefan Agner2021-01-041-8/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There might be hardware configurations where 64-bit data accesses to NVMe registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit NVMe registers, similarly as it is done in Linux kernel. This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC based board, where the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. nvme_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail probing. This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq"). Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Cc: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
| * Merge tag 'u-boot-imx-20201227' of ↵Tom Rini2020-12-281-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2021.1 ---------------- CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680 - fixes for Variscite dart6ul - imx8mp : increase malloc area - fixes for bx50v3 - imx8m: HS400ES and UHS for EVK - imx8qm-rom7720: fix phy bind
| | * i2c: mxc_i2c: improve error message readabilityMarc Ferland2020-12-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use 0x%2lx to print the i2c bus base address in hexadecimal format instead of printing as an integer. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"Pali Rohár2020-12-281-3/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 828d32621686aec593076d16445d39b9b8d49c05. This change revers code which asserting PERST# signal when unloading driver. Driver's remove callback is still there as it is used for other functionality. Asserting PERST# signal prior booting kernel is causing that A3720 boards (Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and 4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900) and anymore. When PERST# signal is not asserted these cards are detected correctly. As this is regression for existing stable Linux kernel versions revert this problematic change in U-Boot. To make cards working with OpenWRT 4.14 kernel it is needed to disable link training prior booting kernel, which is already done in driver's remove callback. Described issue is in Linux kernel pci aardvark driver which is (hopefully) fixed in latest upstream versions. Latest upstream versions should be able to initialize PCIe bus and detects cards independently of the link training and PERST# signal state. So with this change, U-Boot on A3720 boards should be able to boot OpenWRT 4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini2020-12-188-136/+944
| |\
| | * mtd: spi-nor-ids: add Micron MT25QL01G flashHongwei Zhang2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: ca_sflash: Add CAxxxx SPI Flash ControllerPengpeng Chen2020-12-183-0/+585
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Add mem_opsSean Anderson2020-12-181-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The designware ssi device has "broken" chip select behaviour [1], and needs specific manipulation to use the built-in chip select. The existing fix is to use an external GPIO for chip select, but typically the K210 has SPI3 directly connected to a flash chip with dedicated pins. This makes it impossible to use the spi_xfer function to use spi, since the CS is de-asserted in between calls. This patch adds an implementation of exec_op, which gives correct behaviour when reading/writing spi flash. This patch also rearranges the headers to conform to U-Boot style. [1] https://lkml.org/lkml/2015/12/23/132 Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Add support for multiple CTRLR0 layoutsSean Anderson2020-12-181-35/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/ Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Rearrange struct dw_spi_privSean Anderson2020-12-181-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This should reduce the size of the struct, and also groups more similar fields together. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Remove spi_enable_chipSean Anderson2020-12-181-11/+6
| | | | | | | | | | | | | | | | | | | | | This function does nothing but wrap dw_write. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| | * spi: dw: Rename registers to match datasheetSean Anderson2020-12-181-9/+9
| | | | | | | | | | | | | | | | | | | | | A few registers had slightly different names from what is in the datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2025-09-27 11:56:58 +0000