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* | Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2021-01-2525-12/+2709
|\ \ | |/ |/| | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
| * reset: reset-mtmips: add DM_FLAG_PRE_RELOC flagWeijie Gao2021-01-241-0/+1
| | | | | | | | | | | | | | | | | | Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can be probed before relocation even if u-boot,dm-pre-reloc is not present in the dts. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: assign plat->cfg.f_max with a correct valueWeijie Gao2021-01-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | Currently this driver does not set the value of plat->cfg.f_max, which results in that MMC framework will always run at the lowest frequency. This patch sets plat->cfg.f_max to the maximum allowed frequency, which equals to the source clock frequency. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCsWeijie Gao2021-01-241-3/+118
| | | | | | | | | | | | | | | | | | | | | | The driver is missing pad control settings (pad delay and pad conf) for the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will encounter CRC error on data transfers. This patch adds default pad control settings for mt7620_compat. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: fix sclk cycles shift valueWeijie Gao2021-01-241-9/+4
| | | | | | | | | | | | | | | | | | | | | | It turns out that the sclk cycles used by mt7620/mt7628 is the same as other chips (20 bits, 1048576), not 65536. This patch removes sclk_cycle_shift from dev_comp, and uses a macro with a value 20 instead. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: add ethernet driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+1235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: add USB PHY driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+118
| | | | | | | | | | | | | | This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: add spi controller support for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * gpio: add GPIO controller driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+155
| | | | | | | | | | | | | | | | This patch adds GPIO controller driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * watchdog: add watchdog driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+150
| | | | | | | | | | | | | | | | This patch adds watchdog support for the Mediatek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * pinctrl: mtmips: add support for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+210
| | | | | | | | | | | | | | | | This patch adds pinctrl support for MediaTek MT7620 SoC. The MT7620 SoC supports only pinmux. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * clk: add clock driver for MediaTek MT7620 SoCWeijie Gao2021-01-242-0/+160
| | | | | | | | | | | | | | | | | | This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: add uart driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds uart support for MediaTek MT7620 and earlier SoCs. The UART used by MT7620 is incompatible with the ns16550a driver. All registers of this UART have different addresses. A special 16-bit register for Divisor Latch is used to set the baudrate instead of the original two 8-bit registers (DLL and DLM). The driver supports of-platdata which is useful for tiny SPL. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | Merge tag 'u-boot-imx-20210125' of ↵Tom Rini2021-01-257-7/+136
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Changes for 2020.04 ------------------- - new board: Phytec phyCORE-i.MX8MP i.MX8MN Beacon EmbeddedWorks devkit - Fixes: several nanbcb fixes fix for imx8mm_beacon - further switch to distro boot commands - DM: DM Ether for MX6UL CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
| * | spi: imx: Use clock framework if enabledMarek Vasut2021-01-231-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the clock framework is enabled, enable the SPI controller clock and obtain max frequency from the clock framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
| * | spi: imx: Define register bits in the driverMarek Vasut2021-01-231-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
| * | clk: imx: Add ECSPI to iMX8MNMarek Vasut2021-01-231-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | spi: nxp_fspi: Enable support for nxp,imx8mm-fspiAdam Ford2021-01-231-0/+9
| | | | | | | | | | | | | | | | | | | | | The i.MX8M Mini can use the FlexSPI driver. Add support for it to the driver. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | mmc: fsl_esdhc_imx.c: fix compiler warningHeiko Schocher2021-01-231-0/+2
| | | | | | | | | | | | | | | | | | | | | prevent unsued variable compiler warning if DM_REGULATOR is not set. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | w1: mxc: fix buildMartin Fuzzey2021-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that header files no longer include common.h it must be included first. Otherwise the build fails with errors like include/asm/arch/clock.h:43:1: error: unknown type name 'u32' u32 imx_get_uartclk(void); Fixes: c3dc39a2f85b ("arm: Don't include common.h in header files") Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | imx: imx8mn_evk: correct stack/malloc adressPeng Fan2021-01-231-4/+4
| | | | | | | | | | | | | | | | | | | | | Move SP to end of OCRAM space. Drop MALLOC_F to make it alloc from stack space. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | imx: ddr: imx8m: Move selfref_en after DDR scrubYe Li2021-01-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge tag 'u-boot-atmel-2021.04-b' of ↵Tom Rini2021-01-253-18/+161
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.04 cycle This feature set includes macb updates for all interfaces and new sama7g5 variant support; micrel ksz9031 DLL support; a new board from Giant based on Adafruit feather form factor which contains a SAMA5D27 SoC; several fixes regarding the NAND flash PMECC block; and pincontrol drive strength support for pio4 controller.
| * | net: macb: take into account all RGMII interface typesClaudiu Beznea2021-01-221-1/+4
| | | | | | | | | | | | | | | | | | | | | Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add support for sama7g5 emacClaudiu Beznea2021-01-221-0/+9
| | | | | | | | | | | | | | | | | | Add support for SAMA7G5 EMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add support for sama7g5 gmacClaudiu Beznea2021-01-221-0/+33
| | | | | | | | | | | | | | | | | | Add support for SAMA7G5 GMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: check clk_set_rate return value to be negativeClaudiu Beznea2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444de157 ("dm: net: macb: Implement link speed change callback") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add user io config data structureClaudiu Beznea2021-01-221-12/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | pinctrl: at91-pio4: implement drive strength supportEugen Hristev2021-01-221-0/+8
| | | | | | | | | | | | | | | | | | | | | Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | pinctrl: at91-pio4: convert to dev_read_propEugen Hristev2021-01-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use dev_read_prop instead of using the fdt_read_property which reads from the GD struct's fdt. This way the node is accessed via the device config instead of the global struct, which makes code more portable and GD independent. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | net: phy: micrel: fix typoClaudiu Beznea2021-01-191-1/+1
| | | | | | | | | | | | | | | | | | Fix typo. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: phy: micrel: add support for DLL setup on ksz9131Claudiu Beznea2021-01-191-1/+62
| | | | | | | | | | | | | | | | | | Add support for DLL setup on KSZ9131. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.gitTom Rini2021-01-221-56/+0
|\ \ \ | |_|/ |/| |
| * | mmc: exynos_dw_mmc: remove unused functionJaehoon Chung2021-01-131-56/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove unused function in exynos_dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | pci: Add Rockchip dwc based PCIe controller driverShawn Lin2021-01-214-0/+890
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHYShawn Lin2021-01-213-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Rockchip Synopsys based PCIe 3.0 PHY driver as part of Generic PHY framework. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | mmc: xenon_sdhci: Remove duplicated macrosMichal Simek2021-01-201-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to define the same macros in drivers. All macros have been added by commit 17a42abb40dd ("mmc: Define timing macro's"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | net: dwc_eth_qos: Pad descriptors to cacheline sizeMarek Vasut2021-01-191-78/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words after the descriptor. Use this to pad the descriptors to cacheline size and remove the need for noncached memory altogether. Moreover, this lets Tegra use the generic cache flush / invalidate operations. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | | net: ks8851: Reset internal RXFC count on bad packetMarek Vasut2021-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A sporadic condition occurs when the "bad packet" error is triggered repeatedly, which results in "bad packet" messages scrolling on the console during transfer. To avoid triggering this, reset the internal RXFC count on the first occurance of the "bad packet", which forces the code to re-read the RX packet count from the MAC, and prevents any additional "bad packet" messages if there are no more packets in the MAC. Also print better debug information if this condition occurs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com>
* | | net: ftgmac100: Read and retain MAC addressHongwei Zhang2021-01-191-0/+32
| | | | | | | | | | | | | | | | | | Read and retain MAC address across flash and QEMU support. Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
* | | net: e1000: implement eth_write_hwaddr for DM_ETHIan Ray2021-01-191-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement programming MAC address to the hardware also for device model configuration. Fixes: b565b18a294f ("board: ge: bx50v3: Enable DM for PCI and ethernet") Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* | | timer: mtk_timer: initialize the timer before useWeijie Gao2021-01-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | | pinctrl: mediatek: correct error handlingHeinrich Schuchardt2021-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no GPIO controller is found, the return value should not depend on a random value on the stack. Initialize variable ret. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | | mtd: remove drivers/mtd/mw_eeprom.cHeinrich Schuchardt2021-01-182-239/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write() and mw_eeprom_read() have incorrect loop conditions: while (len <= 2) { CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | drivers: qe: avoid double free()Heinrich Schuchardt2021-01-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Avoid calling free(addr) twice if the device for ucode is not found. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | mmc: fsl_esdhc_spl: remove superfluous free()Heinrich Schuchardt2021-01-181-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | dma: bcm6348: incorrect buffer allocationHeinrich Schuchardt2021-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling calloc() for 0 members does not make any sense. Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally unreasonable. The current code will lead to a NULL dereference in bcm6348_iudma_enable(). The assignments for ch_priv->busy_desc are obviously swapped. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | power: pmic: add driver for Monolithic Power mp5416Tim Harvey2021-01-183-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | This adds basic register access and child regulator binding for the Monolithic MP5416 Power Management IC which integrates four DC/DC switching converters and five LDO regulators. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | | aspeed: Add AST2600 platform supportChia-Wei, Wang2021-01-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | reset: aspeed: Add AST2600 reset supportChia-Wei, Wang2021-01-183-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
generated by cgit (git 2.34.1) at 2025-09-26 18:28:33 +0000