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* Merge git://git.denx.de/u-boot-marvellTom Rini2018-01-102-5/+5
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| * pinctrl: mvebu: Make drivers depend on the pinctrl frameworkMiquel Raynal2018-01-091-2/+2
| | | | | | | | | | | | | | | | | | Armada pinctrl drivers shall not be compiled without the entire pinctrl framework and thus lack a "depends on" condition, otherwise the driver will simply not be probed. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCsMiquel Raynal2018-01-091-3/+3
| | | | | | | | | | | | | | | | | | | | Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus did not benefit from Ethernet support. Add ARMADA_3700 in the "depends on" list of the MVNETA Kconfig entry. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | PCI: Drop CONFIG_TSI108_PCITuomas Tynkkynen2018-01-102-168/+0
| | | | | | | | | | | | | | Last user of this option went away in 2015 in commit: d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support") Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
* | ram: stm32: add memory mapping selection supportPatrice Chotard2018-01-101-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to controls the memory internal mapping at address 0x0000 0000. We can either map at 0x0000 0000 : _ main flash memory _ system flash memory _ FMC bank1 (NOR/PSRAM 1 and 2) _ embedded SRAM _ FMC/SDRAM bank1 This is needed for future STM32F469-disco board Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driverPatrice Chotard2018-01-102-183/+0
| | | | | | | | | | | | | | | | | | | | | | Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers instead of board GPIO initialization. Remove stm32_gpio.c which is no more used and migrate structs stm32_gpio_regs and stm32_gpio_priv into arch-stm32f4/gpio.h to not break compilation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | board: stm32f429-disco: switch to DM STM32 clock driverPatrice Chotard2018-01-101-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Use available DM clk_stm32f.c driver instead of dedicated mach-stm32/stm32f4/clock.c. Migrate periph_clock defines from stm32_periph.h directly in CLK driver. These periph_clock defines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK. Enable also CLK flag. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | board: stm32f429-disco: switch to DM STM32 serial driverPatrice Chotard2018-01-101-117/+0
| | | | | | | | | | | | | | | | | | | | | | Remove serial_stm32.c driver and uart init from board file, use available DM serial_stm32x7.c driver compatible for STM32F4/F7 and H7 SoCs. The serial_stm32x7.c driver will be renamed later with a more generic name as it's shared with all STM32 Socs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | pinctrl: stm32: add stm32f4 pinctrl compatible stringsPatrice Chotard2018-01-101-0/+2
| | | | | | | | | | | | | | | | | | STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | rockchip: clk: bind reset driverElaine Zhang2018-01-098-0/+70
| | | | | | | | | | | | | | | | | | Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: reset: support a (common) rockchip reset driversElaine Zhang2018-01-093-0/+143
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Create driver to support the soft reset (i.e. peripheral) of all Rockchip SoCs. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed commit tag:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge git://git.denx.de/u-boot-imxTom Rini2018-01-082-4/+2
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| * mtd: nand: mxs_nand_spl: Remove nand size printJagan Teki2018-01-081-2/+0
| | | | | | | | | | | | | | It is not much needed to print nand size in SPL during nand boot, and most of nand spl drivers doesn't print the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mx6ull: Handle the CONFIG_MX6ULL cases correctlyFabio Estevam2018-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Breno Lima <breno.lima@nxp.com> Tested-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
* | crypto/fsl: fix BLOB encapsulation and decapsulationClemens Gruber2018-01-081-14/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command" To ensure coherency, we require the key_mod, src and dst buffers to be aligned to the cache line size and flush/invalidate the memory regions. The same requirements apply to the job descriptor. Tested on an i.MX6Q board. Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
* | video: Support multiple lines version string displayPeng Fan2018-01-031-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | The calculation of left space for version string is not correct, should use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space than actual have and cause string to overlay logo picture. Also current version string display only supports two lines words at max. This also causes overlay when the LCD pixel column size is not enough. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Anatolij Gustschin <agust@denx.de>
* | video: ipu: Fix dereferencing NULL pointer problemPeng Fan2018-01-031-1/+5
|/ | | | | | | | The clk_set_rate function dereferences the clk pointer without checking whether it is NULL. This may cause problem when clk is NULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* power: tps65910: replace error() by pr_err()Felix Brack2018-01-012-4/+4
| | | | | | | | | | The patch replaces the former error() by the new pr_err(). This makes the TPS65910 driver conform to Masahiro's patch 'treewide:replace with error() with pr_err()' introduced October 2017. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-spiTom Rini2017-12-191-0/+1
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| * mtd/spi: fix block count for is25lq040bSean Nyekjaer2017-12-191-1/+1
| | | | | | | | | | | | | | | | This spi-nor is 4Mbit/512KB Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b") Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * mtd/spi: add support for is25lq040bSean Nyekjaer2017-11-211-0/+1
| | | | | | | | | | Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2017-12-193-10/+23
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| * | sunxi: Fix A20-OLinuXino-MICRO LAN8710 supportStefan Mavrodiev2017-12-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: video: HDMI: split VSYNC and HSYNC polarity settingsVasily Khoruzhick2017-12-021-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are actually different bits, and since some monitors (Benq BL2420PT) have modes with different HSYNC and VSYNC polarity, we should set them independently Tested on Pine64-LTS with Benq BL2420PT monitor. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | video: sunxi: de2: add support for LCD SimpleFBIcenowy Zheng2017-12-021-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for setting up SimpleFB for LCD display output in DE2 SimpleFB setup code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-12-182-4/+7
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| * | | armv8: ls1043a/ls2080a: check SoC by device IDWenbin song2017-12-132-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | net: phy: meson-gxl: detect LPA corruptionJerome Brunet2017-12-181-1/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is ported from the Linux patch posted at [1] and applied to net tree as commit f1e2400a80ff. The purpose of this change is to fix the incorrect detection of the link partner (LP) advertised capabilities which sometimes happens with this PHY (roughly 1 time in a dozen) This issue may cause the link to be negotiated at 10Mbps/Full or 10Mbps/Half when 100MBps/Full is actually possible. In some case, the link is even completely broken and no communication is possible. To detect the corruption, we must look for a magic undocumented bit in the WOL bank (hint given by the SoC vendor kernel) but this is not enough to cover all cases. We also have to look at the LPA ack. If the LP supports Aneg but did not ack our base code when aneg is completed, we assume something went wrong. The detection of a corrupted LPA triggers a restart of the aneg process. This solves the problem but may take up to 6 retries to complete. [1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com Fixes: 8995a96d1d67 ("net: phy: Add Amlogic Meson GXL Internal PHY support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | | Merge tag 'xilinx-for-v2018.01-rc2-v2' of ↵Tom Rini2017-12-182-0/+22
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.01-rc2-v2 fpga: - Enable loading bitstream via fit image for !xilinx platforms zynq: - Fix SPL SD boot mode zynqmp: - Not not reset in panic - Do not use simple allocator because of fat changes - Various dt chagnes - modeboot variable setup - Fix fpga loading on automotive devices - Fix coverity issues test: - Fix env test for !hush case - Stephen's patch
| * | | | fpga: allow programming fpga from FIT image for all FPGA driversGoldschmidt Simon2017-12-142-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This drops the limit that fpga is only loaded from FIT images for Xilinx. This is done by moving the 'partial' check from 'common/image.c' to 'drivers/fpga/xilinx.c' (the only driver supporting partial images yet) and supplies a weak default implementation in 'drivers/fpga/fpga.c'. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | Merge git://git.denx.de/u-boot-dmTom Rini2017-12-149-6/+589
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| * | | | | power: pmic/regulator: Add basic support for TPS65910Felix Brack2017-12-126-0/+575
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Texas Instrument's TPS65910 PMIC contains 3 buck DC-DC converts, one boost DC-DC converter and 8 LDOs. This patch implements driver model support for the TPS65910 PMIC and its regulators making the get/set API for regulator value/enable available. This patch depends on the patch "am33xx: Add a function to query MPU voltage in uV" to build correctly. For boards relying on the DT include file tps65910.dtsi the v3 patch "power: extend prefix match to regulator-name property" and an appropriate regulator naming is also required. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | | dm: blk: Use uclass_find_first/next_device() in blk_first/next_device()Stefan Roese2017-12-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the calls to uclass_first/next_device() in blk_first/ next_device() to use uclass_find_first/next_device() instead. These functions don't prepare the devices, which is correct in this case. With this patch applied, the "usb storage" command now works again as expected: => usb storage Device 0: Vendor: SanDisk Rev: 1.00 Prod: Ultra Type: Removable Hard Disk Capacity: 58656.0 MB = 57.2 GB (120127488 x 512) Without this patch, it used to generate this buggy output: => usb storage Card did not respond to voltage select! mmc_init: -95, time 26 No storage devices, perhaps not 'usb start'ed..? Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | | power: extend prefix match to regulator-name propertyFelix Brack2017-12-121-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends pmic_bind_children prefix matching. In addition to the node name the property regulator-name is used while trying to match prefixes. This allows assigning different drivers to regulator nodes named regulator@1 and regulator@10 for example. I have discarded the idea of using other properties then regulator-name as I do not see any benefit in using property compatible or even regulator-compatible. Of course I am open to change this if there are good reasons to do so. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | | dm: reset: have the reset-command perform a COLD resetPhilipp Tomsich2017-12-121-1/+1
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DM version of do_reset has been issuing a warm-reset, which (on some platforms keeps GPIOs and other parts of the platform active). This may cause unintended behaviour, as calling do_reset usually indicates a desire to reset the board/platform and not just the CPU. This changes do_reset to always request a COLD reset. Note that programmatic uses can still invoke a WARM reset through reset_cpu() or using sysreset_walk(). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2017-12-131-8/+5
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| * | | | | usb: r8a66597: convert wait loop to readw_poll_timeoutChris Brandt2017-12-091-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is better to use an existing wait loop implementation. Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
* | | | | | Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini2017-12-1311-8/+4750
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| * | | | | net: ravb: Add R8A77995 D3 compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the Ethernet AVB driver for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | net: ravb: Add R8A77970 V3M compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the Ethernet AVB driver for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | mmc: uniphier-sd: Add R8A77995 D3 compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the Uniphier SD driver for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | mmc: uniphier-sd: Add R8A77970 V3M compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the Uniphier SD driver for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | gpio: rmobile: Add generic Gen3 compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic compatible to the GPIO driver for Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | gpio: rmobile: Add R8A77995 D3 compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the GPIO driver for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | gpio: rmobile: Add R8A77970 V3M compatibleMarek Vasut2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to the GPIO driver for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | pinctrl: rmobile: Add R8A77995 D3 PFC tablesMarek Vasut2017-12-095-0/+1837
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PFC tables for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | pinctrl: rmobile: Add R8A77970 V3M PFC tablesMarek Vasut2017-12-095-0/+2620
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PFC tables for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | clk: rmobile: Add R8A77995 D3 clock tablesMarek Vasut2017-12-091-3/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock tables for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | clk: rmobile: Add R8A77970 V3M clock tablesMarek Vasut2017-12-092-4/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock tables for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | clk: rmobile: Fix typo in R8A7796 RPC clock table entryMarek Vasut2017-12-091-1/+1
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a copy-paste typo in the clock table entry, s/7795/7796/. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit (git 2.34.1) at 2024-09-21 12:25:57 +0000