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* reset: reset-mtmips: add DM_FLAG_PRE_RELOC flagWeijie Gao2021-01-241-0/+1
| | | | | | | | | Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can be probed before relocation even if u-boot,dm-pre-reloc is not present in the dts. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* reset: aspeed: Add AST2600 reset supportChia-Wei, Wang2021-01-183-0/+118
| | | | | | | | Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* reset: stm32-reset: migrate trace to dev and log macroPatrick Delaunay2021-01-131-4/+9
| | | | | | | | | | Change debug to dev_dbg macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-056-6/+10
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Access device ofnode through functionsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Use access methods for dev/uclass private dataSimon Glass2021-01-054-4/+8
| | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-052-2/+2
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2020-12-092-2/+2
| | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-131-2/+2
| | | | | | | | | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-1320-20/+20
|/ | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* reset: stm32: Add support of MCU HOLD BOOTPatrick Delaunay2020-11-251-4/+13
| | | | | | | | | | | | | | | Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* cosmetic: reset: ast2500: Rename driver and configsChia-Wei, Wang2020-10-223-2/+2
| | | | | | | | | | 1. Rename AST2500 reset driver from ast2500-reset.c to reset-ast2500.c 2. Rename AST2500 reset kconfig option from AST2500_RESET to RESET_AST2500 Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-222-51/+55
| | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* dm: add cells_count parameter in *_count_phandle_with_argsPatrick Delaunay2020-10-061-1/+2
| | | | | | | | | | | | | | | | | | | The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* reset: add reset controller driver for SCMI agentsEtienne Carriere2020-09-303-0/+90
| | | | | | | | | | | | | | | | | | | This change introduces a reset controller driver for SCMI agent devices. When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent binds a reset controller device for each SCMI reset domain protocol devices enabled in the FDT. SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Reset Domain protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* test: reset: Add tests for the managed APIJean-Jacques Hiblot2020-09-302-6/+64
| | | | | | | | | The tests are basically the same as for the regular API. Except that the reset are initialized using the managed API, and no freed manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* drivers: reset: Add a managed API to get reset controllers from the DTJean-Jacques Hiblot2020-09-301-4/+114
| | | | | | | | | | | | | | Add managed functions to get a reset_ctl from the device-tree, based on a name or an index. Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl) from the device-tree. When the device is unbound, the reset controllers are automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
* reset: Add IPQ40xx reset controller driverRobert Marko2020-09-183-0/+182
| | | | | | | | On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()Masahiro Yamada2020-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To help this tedious work, this commit converts devfdt_get_addr_ptr() to dev_read_addr_ptr() by coccinelle. I also removed redundant casts because dev_read_addr_ptr() returns an opaque pointer. To generate this commit, I ran the following semantic patch excluding include/dm/. <smpl> @@ type T; expression dev; @@ -(T *)devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) @@ expression dev; @@ -devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* configs: reset: fu540: enable dm reset framework for SiFiveSagar Shrikant Kadam2020-08-042-0/+10
| | | | | | | | | | Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam2020-08-041-0/+118
| | | | | | | | | | | | | | | | PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-241-1/+1
| | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* reset: Add Raspberry Pi 4 firmware reset controllerNicolas Saenz Julienne2020-07-103-0/+72
| | | | | | | | | | | Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* reset: Add generic reset driverSean Anderson2020-07-013-0/+87
| | | | | | | | | | | This patch adds a generic reset driver. It is designed to be useful when one has a register in a regmap which contains bits that reset other devices. I thought this seemed like a very generic use, so here is a generic driver. The overall structure has been modeled on the syscon-reboot driver. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-1811-0/+11
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-1820-0/+20
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers/reset/Kconfig: fix typoTrevor Woerner2020-05-151-1/+1
| | | | Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_STM32 -> CONFIG_ARCH_STM32Trevor Woerner2020-05-151-1/+1
| | | | | | Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2020-02-1119-18/+41
|\ | | | | | | | | | | | | sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
| * dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-0518-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Require users of devres to include the headerSimon Glass2020-02-053-0/+3
| | | | | | | | | | | | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * reset: Rename free() to rfree()Simon Glass2020-02-0518-18/+18
| | | | | | | | | | | | | | | | This function name conflicts with our desire to #define free() to something else on sandbox. Since it deals with resources, rename it to rfree(). Signed-off-by: Simon Glass <sjg@chromium.org>
* | reset: socfpga: Poll for reset status after deassert resetLey Foon Tan2020-02-031-1/+5
|/ | | | | | | | | | | In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue. Retry with this fix more than 10 times without issue. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ARC: HSDK: introduce reset driverEugeniy Paltsev2019-11-013-0/+124
| | | | | | | Introduce reset driver for Synopsys ARC HSDK SoC Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* reset: add reset controller driver for MediaTek MIPS platformWeijie Gao2019-10-253-0/+90
| | | | | | | This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* imx: add support for i.MX7/i.MX8MQ reset controllerPatrick Wildt2019-10-083-0/+320
| | | | | | | | | | Add support for the reset controller that's used on the i.MX7D and i.MX8MQ. This will be needed to be able to assert the PCIe reset pins. Bindings taken from Linux, driver implementation mostly taken from Linux and adjusted to U-Boot infrastructure. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* env: Move env_get() to env.hSimon Glass2019-08-111-0/+1
| | | | | | | Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* sysreset: add support for socfpga sysresetSimon Goldschmidt2019-07-211-0/+19
| | | | | | | | | | This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga to a UCLASS_SYSRESET based dm driver. A side effect is that gen5 and a10 can now select between cold and warm reset. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* reset: socfpga: convert to livetreeSimon Goldschmidt2019-05-101-3/+1
| | | | | | | Convert 'socfpga_reset_probe' to use 'dev_read_u32_default' instead of 'fdtdec_get_int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-05-081-17/+36
|\ | | | | | | | | | | | | | | | | - H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
| * reset: Get the RESET by index without deviceJagan Teki2019-05-091-17/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rockchip: use 'arch-rockchip' as header file pathKever Yang2019-05-011-1/+1
| | | | | | | | | | | | | | | | Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogicTom Rini2019-04-241-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
| * | reset-meson: Add AXG reset compatibleNeil Armstrong2019-04-101-0/+1
| |/ | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | reset: add reset driver for HiSilicon platformShawn Guo2019-04-233-0/+110
| | | | | | | | | | | | | | | | | | It adds a Driver Model compatible reset driver for HiSlicon platform. The driver implements a custom .of_xlate function, and uses .data field as reset register offset and .id field as bit shift. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | reset: socfpga: add reset handling for old kernelsSimon Goldschmidt2019-04-171-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL. However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround. This workaround is implemented in the 'assert' and 'remove' callbacks of this reset driver: the 'assert' callback does not disable peripherals that were already taken out of reset, while the 'remove' callback, which is called on OS_PREPARE, deasserts all peripheral resets if the environment variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5 SPL did up to now. This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
generated by cgit (git 2.34.1) at 2024-06-27 09:44:30 +0000