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path: root/drivers/pci/pci-uclass.c
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* dm: pci: Use a 1:1 mapping for bus <-> phy addressesChristian Gmeiner2018-06-131-0/+10
| | | | | | | | | | | | | | | | | If U-Boot gets used as coreboot payload all pci resources got assigned by coreboot. If a dts without any pci ranges gets used the dm is not able to access pci device memory. To get things working make use of a 1:1 mapping for bus <-> phy addresses. This change makes it possible to get the e1000 U-Boot driver working on a sandybridge device where U-Boot is used as coreboot payload. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed 'u-boot' in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: pci: Make ranges dt property optionalChristian Gmeiner2018-06-131-13/+10
| | | | | | | | | | | | | | | If we use U-Boot as coreboot payload with a generic dts without any ranges specified we fail in pci pre_probe and our pci bus is not usable. So convert decode_regions(..) into a void function and do the simple error handling there. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed 'u-boot' in the commit message and checkpatch warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not setTuomas Tynkkynen2018-05-261-0/+7
| | | | | | | | | | | | | | | | | Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with the 'highmem=off' parameter passed to QEMU's virt machine. The reason is that when 'highmem' is not disabled, QEMU appends 64-bit a memory resource to the PCI controller's regions property in DT in addition to the 32-bit PCI memory window in low memory. And the current DT parsing code picks the last (thus the 64-bit one) memory resource, whose address eventually gets silently truncated to 32 bits because CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break. Avoid this problem by ignoring memory regions whose addresses are above the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: pci: Avoid setting a PCI region that has 0 sizeBin Meng2018-03-301-2/+3
| | | | | | | It makes no sense to set a PCI region that has 0 size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: pci: Check board information pointer in decode_regions()Bin Meng2018-03-301-0/+3
| | | | | | | | | | | | PCI enumeration may happen very early on an x86 board. The board information pointer should have been checked in decode_regions() as its space may not be allocated yet. With this commit, Intel Galileo board boots again. Fixes: 664758c ("pci: Fix decode regions for memory banks") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: Fix decode regions for memory banksBernhard Messerklinger2018-02-231-1/+16
| | | | | | | | Since memory banks may not be located behind each other we need to add them separately. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* pci: Add helper for implementing memory-mapped config space accessesTuomas Tynkkynen2017-10-061-0/+58
| | | | | | | | | | This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: ofnode: rename ofnode_read_prop() to ofnode_get_property()Masahiro Yamada2017-07-111-1/+1
| | | | | | | | | | | | | This function returns the pointer to the value of a node property. The current name ofnode_read_prop() is confusing. Follow the naming of_get_property() from Linux. The return type (const u32 *) is wrong. DT property values can be strings as well as integers. This is why of_get_property/fdt_getprop returns an opaque pointer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: core: Add functions to obtain node's address/size cellsSimon Glass2017-07-111-3/+3
| | | | | | | | | | | | | | | | The of_n_addr_cells() and of_n_size_cells() functions are useful for getting the size of addresses in a node, but in a few places U-Boot needs to obtain the actual property value for a node without walking up the stack. Add functions for this and just the existing code to use it. Add a comment to the existing ofnode functions which do not do the right thing with a flat tree. This fixes a problem reading PCI addresses. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1
* dm: pci: Update uclass to support livetreeSimon Glass2017-06-011-14/+12
| | | | | | | Update the PCI uclass to support livetree. This mostly involves fixing the address decoding from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: avoid memory leakxypron.glpk@gmx.de2017-05-121-0/+1
| | | | | | | | | | | strdup uses malloc to allocate memory for str. If we cannot bind to the generic driver we should release the memory. The problem was indicated by clang scan-build. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: correct a function descriptionHou Zhiqiang2017-03-261-2/+3
| | | | | | | | | In the description of function pci_match_one_id(), there are some problems on arguments list and return value description, so correct them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Replace of_offset with accessorSimon Glass2017-02-081-4/+5
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Flip condition for detecting non-PCI parent devicesPaul Burton2016-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pci_uclass_pre_probe an attempt is made to detect whether the parent of a device is a PCI device and that the device is thus a bridge. This was being done by checking whether the parent of the device is of the UCLASS_ROOT class. This causes problems if the PCI controller is a child of some other non-PCI node, for example a simple-bus node. For example, if the device tree contains something like the following then pci_uclass_pre_probe would incorrectly believe that the PCI controller is a bridge, with a PCI parent: / { some_child { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <>; pci_controller: pci@10000000 { compatible = "my-pci-controller"; device_type = "pci"; reg = <0x10000000 0x2000000>; }; }; }; Avoid this incorrect detection of bridges by instead checking whether the parent devices class is UCLASS_PCI and treating a device as a bridge when this is true, making use of device_is_on_pci_bus to perform this test. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-271-14/+1
| | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-271-10/+1
| | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Device scanning range fixYoshinori Sato2016-04-251-1/+1
| | | | | | | | The terminal condition in the area where a PCI device is scanned is wrong, and 1f.7 isn't scanned. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Correct a few comments and nitsSimon Glass2016-03-171-1/+0
| | | | | | | | Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add functions to update PCI configuration registersSimon Glass2016-03-171-0/+57
| | | | | | | | | It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-141-3/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* Implement "pci enum" command for CONFIG_DM_PCIStephen Warren2016-01-281-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they are without that config option enabled. No command exists to enumerate the PCI buses. Hence, unless some board-specific code causes PCI enumeration, PCI-based Ethernet devices are not detected, and network access is not available. This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a mechanism whereby PCI can be enumerated. do_pci()'s handling of case 'e' is moved into a single location before the dev variable is assigned, in order to skip calculation of dev. The enum sub-command doesn't need the dev value, and skipping its calculation avoids an irrelevant error being printed. Using a command to initialize PCI like this has a disadvantage relative to enumerating PCI at boot. In particular, Ethernet devices are not probed during PCI enumeration, but only when used. This defers setting variables such as ethact, ethaddr, etc. until the first network-related command is executed. Hopefully this will not cause further issues. Perhaps in the long term, we need a "net start/enum" command too? Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to write a BARSimon Glass2016-01-241-0/+8
| | | | | | | | Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_bus_to_hose() to compatibilitySimon Glass2016-01-241-15/+1
| | | | | | | | This function should not be used by driver-model code, so move it to the compatibility portion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Tidy up comments in pci_bind_bus_devices()Simon Glass2016-01-121-3/+1
| | | | | | | | | The current comments are confusing. We don't actually bind a generic device when the device tree has no information. We try to scan available PCI drivers. Update the comments to reflect this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add driver model API functions for address mappingSimon Glass2016-01-121-0/+136
| | | | | | | | At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to read a PCI BARSimon Glass2016-01-121-0/+13
| | | | | | | Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_class()Simon Glass2016-01-121-0/+20
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_device()Simon Glass2016-01-121-0/+39
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use driver model PCI API in auto-configSimon Glass2016-01-121-14/+5
| | | | | | | | | | | | | At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_bus_find_bdf()Simon Glass2016-01-121-1/+1
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_get_bdf()Simon Glass2016-01-121-4/+5
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to find the regions for a PCI busSimon Glass2015-12-011-0/+30
| | | | | | | | | This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to get the controller for a busSimon Glass2015-12-011-0/+8
| | | | | | | | | A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add functions to emulate 8- and 16-bit accessSimon Glass2015-12-011-0/+39
| | | | | | | | | Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Support decoding ranges with duplicate entriesSimon Glass2015-12-011-3/+10
| | | | | | | | | | | | | | | | | | At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones. There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding). We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Set up the SDRAM mapping correctlySimon Glass2015-12-011-6/+9
| | | | | | | | | | SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-211-0/+18
| | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-211-24/+1
| | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Adjust pci_find_and_bind_driver() to return -EPERMSimon Glass2015-10-211-12/+19
| | | | | | | | | | | | | | The current code returns 0 even if it failed to find or bind a driver. The caller then has to check the returned device to see if it is NULL. It is better to return an error code in this case so that it is clear what happened. Adjust the code to return -EPERM, indicating that the device was not bound because it is not needed for pre-relocation use. Add comments so that the return value is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct a few debug() statementsSimon Glass2015-10-211-2/+2
| | | | | | | | One debug() statement is missing a newline. The other has a repeated word. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Tidy up auto-config error handlingSimon Glass2015-10-211-3/+12
| | | | | | | | | | | When the auto-configuration process fails for a device (generally due to lack of memory) we should return the error correctly so that we don't continue to try memory allocations which will fail. Adjust the code to check for errors and abort if something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-161-2/+2
| | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow a PCI bus to be found without an aliasSimon Glass2015-09-091-4/+24
| | | | | | | | | | | | | | At present, until a PCI bus is probed, it cannot be found by its sequence number unless it has an alias. This is the same with any device. However with PCI this is more annoying than usual, since bus 0 is always the same device. Add a function that tries a little harder to locate PCI bus 0. This means that PCI enumeration will happen automatically on the first access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Optimize pci_uclass_post_bind()Bin Meng2015-08-261-0/+7
| | | | | | | | If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-261-2/+2
| | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-261-0/+21
| | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-261-11/+30
| | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-141-0/+4
| | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-141-0/+60
| | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-10-05 13:06:18 +0000