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path: root/drivers/mmc/fsl_esdhc.c
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* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-131-7/+7
| | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-131-1/+1
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-131-2/+2
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: fsl_esdhc: make sure delay chain locked for HS400Yangbo Lu2020-11-281-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400, db8f936 mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: fsl_esdhc: set sysctl register for clock initializationYangbo Lu2020-11-281-1/+1
| | | | | | | | | The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: fsl_esdhc: add ADMA2 supportMichael Walle2020-10-141-5/+45
| | | | | | | | | | | Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
* mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle2020-10-141-73/+65
| | | | | | | Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
* mmc: fsl_esdhc: simplify esdhc_setup_data()Michael Walle2020-10-121-27/+42
| | | | | | | | First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc>
* mmc: fsl_esdhc: use dma-mapping APIMichael Walle2020-10-121-35/+14
| | | | | | | Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc>
* mmc: fsl_esdhc: simplify 64bit check for SDMA transfersMichael Walle2020-10-121-23/+6
| | | | | | | | | | SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc>
* mmc: fsl_esdhc: fix eMMC HS400 stability issueYangbo Lu2020-10-121-1/+4
| | | | | | | | | | | | | | | | | | | | | There was a fix-up for eMMC HS400 stability issue in Linux. Patch link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53 Description: Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Introduce the fix-up in u-boot since the issue could be reproduced in u-boot too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: fix mmc->clock with actual clockYangbo Lu2020-10-121-0/+3
| | | | | | | | Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock which was removed accidentally. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu2020-10-121-34/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during initYangbo Lu2020-10-121-0/+3
| | | | | | | Clean TBCTL[TB_EN] manually during init since it is not able to be reset by reset all operation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: support tuning for eMMC HS200Yangbo Lu2020-10-121-3/+103
| | | | | | Support tuning process for eMMC HS200 for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: add a reinit() callbackYangbo Lu2020-10-121-0/+9
| | | | | | | Add a reinit() callback for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* Move eSDHC adapter card identification to board filesYangbo Lu2020-07-271-38/+0
| | | | | | | | | | | | | | | | The eSDHC adapter card identification and multiplexing configuration through FPGA had been implemented in both common mmc driver and fsl_esdhc driver. However it is proper to move these code to board files and do it during board initialization. The FPGA registers are also board specific. This patch is to move eSDHC adapter card identification and multiplexing configuration from mmc driver to specific board files. And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Drop global data sdhc_adapter for powerpcYangbo Lu2020-07-271-1/+0
| | | | | | | | | | The sdhc_adapter of global data has not been used, and we do not have to use it as global data even we may need it in the future. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability issueYangbo Lu2020-06-151-2/+36
| | | | | | | | | | | | | | | | | | | | When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface runs, the more damage accumulates. This issue now is found on LX2160A eSDHC1 for only SD card. The hardware workaround is recommended to use an on-board level shifter that is 1.8v on SoC side and 3.3v on SD card side. For boards without hardware workaround, this option could be enabled, ensuring 1.8v IO voltage and disabling eSDHC if no card. This option assumes no hotplug, and u-boot has to make all the way to to linux to use 1.8v UHS-I speed mode if has card. If you do not want the workaround for better user experience, of course you can choose to not select it running eSDHC in unsafe mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* mmc: fsl_esdhc: read register once for card inserted statusYangbo Lu2020-06-151-5/+4
| | | | | | | No need to poll register for card inserted status. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: fsl_esdhc: actually enable cache snooping on mpc830xRasmus Villemoes2020-02-191-2/+13
| | | | | | | | | | | | | | | | | | | The reference manuals for MPC8308 and MPC8309 both say that the esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the System configuration registers. Unfortunately, that doesn't mean that the registers are just mirrors of each other - any write to esdhcctl is simply ignored. So to actually enable cache snooping, we unfortunately have to add a little ifdeffery. There is, naturally, no description of the bit fields of esdhcctl in the MPC8309 manual, but comparing the description of esdhcctl from the LS1021A reference manual to the description of the sdhccr in MPC8309, one also finds that the fields are bit-reversed, so the bit to set is 0x02000000 rather than 0x00000040 - this is also what board_mmc_init() uses in the two gdsys/mpc8308/ boards. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-051-0/+1
| | | | | | | | | | | | At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2020-01-161-10/+22
| | | | | | | | | | | | | | The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: drop useless fdt fixupYangbo Lu2020-01-161-9/+0
| | | | | | | | The fdt fixup for properties "peripheral-frequency" and "adapter-type" was once for a Freescale SDK release. The properties haven't been existed in linux mainline. Drop these useless code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | | These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: fsl_esdhc: get clock directly from global dataYangbo Lu2019-11-271-30/+4
| | | | | | | | | | | | This patch is to get clock directly from global data. - Remove uclass clk api method. This was what i.MX platforms were using, while QorIQ platforms weren't. - Get clock only from global data, dropping mxc_get_clock(). QorIQ eSDHC controllers on one silicon use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* mmc: fsl_esdhc: clean up DM and non-DM codeYangbo Lu2019-11-051-104/+100
| | | | | | | | | | | Make DM and non-DM code clear using below structure. #if !CONFIG_IS_ENABLED(DM_MMC) <non-DM_MMC code> #else <DM_MMC code> #endif Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: always check write protect stateYangbo Lu2019-11-051-11/+4
| | | | | | | The QorIQ eSDHC on all platforms supports checking write protect state through register bit. So check it always. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: drop redundant code for non-removable featureYangbo Lu2019-11-051-14/+4
| | | | | | | Drop redundant code for non-removable feature. "non-removable" property has been read in mmc_of_parse(). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common()Yangbo Lu2019-11-051-35/+8
| | | | | | | | The fsl_esdhc_init() was actually to get configuration of mmc_config. So rename it to fsl_esdhc_get_cfg_common() and make it common for both DM_MMC and non-DM_MMC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: clean up bus width configuration codeYangbo Lu2019-11-051-48/+22
| | | | | | | | | | | | | | | | | This patch is to clean up bus width setting code. - For DM_MMC, remove getting "bus-width" from device tree. This has been done in mmc_of_parse(). - For non-DM_MMC, move bus width configuration from fsl_esdhc_init() to fsl_esdhc_initialize() which is non-DM_MMC specific. And fix up bus width configuration to support only 1-bit, 4-bit, or 8-bit. Keep using 8-bit if it's not set because many platforms use driver without providing max bus width. - Remove bus_width member from fsl_esdhc_priv structure. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: fix voltage validationYangbo Lu2019-11-051-26/+10
| | | | | | | | Voltage validation should be done by CMD8. Current comparison between mmc_cfg voltages and host voltage capabilities is meaningless. So drop current comparison and let voltage validation is through CMD8. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init()Yangbo Lu2019-11-051-36/+0
| | | | | | | | Controller initialization is not needed in fsl_esdhc_init(). It will be done in esdhc_init() for non-DM_MMC, and in esdhc_init_common() in probe for DM_MMC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: drop i.MX DDR support codeYangbo Lu2019-10-291-6/+2
| | | | | | | | | | | A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode, and hasn't been supported. Let's drop DDR support code for i.MX in fsl_esdhc driver. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: remove redundant DM_MMC checkingYangbo Lu2019-10-291-2/+0
| | | | | | | Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: make BLK as hard requirement of DM_MMCYangbo Lu2019-10-291-32/+1
| | | | | | | | | | | | | | U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* mmc: fsl_esdhc: Add emmc hs200 supportYinbo Zhu2019-09-121-15/+19
| | | | | | | | | | Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a. This increases eMMC performance. Tuning procedure is currently not supported. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* mmc: fsl_esdhc: drop i.MX codeYangbo Lu2019-06-231-609/+16
| | | | | | | | | Dropped i.MX code which couldn't be reused. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
* mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabledYangbo Lu2019-06-191-0/+29
| | | | | | | | | | | | | | | | | | u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not. config BLK bool "Support block devices" depends on DM default y if DM_MMC When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-1/+4
| | | | | | | | PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-0/+6
| | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"Lukasz Majewski2019-05-201-18/+5
| | | | | | | | | | | | | | | | | | | This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which causes the imx53 HSC to hang as the eMMC is not working properly anymore. The exact error message: MMC write: dev # 0, block # 2, count 927 ... mmc write failed 0 blocks written: ERROR imx53 is not using the DDR mode. Debugging of pre_div and div generation showed that those values are generated in a way, which is not matching the ones from working setup. As the original patch was performing code refactoring, let's revert this change, so all imx53 boards would work again. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* mmc: fsl_esdhc: Fix wp_enable issueYe Li2019-05-031-5/+13
| | | | | | | | | | | The wp-gpios property is used for gpio, if this is set, the WP pin is muxed to gpio function, can't be used as internal WP checking. However the codes remain to use internal WP checking. This patch changes to examine the "fsl,wp-controller" for enabling internal WP checking, and "wp-gpios" for muxing to gpio. Signed-off-by: Ye Li <ye.li@nxp.com>
* mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issueYe Li2019-05-031-5/+18
| | | | | | | | | | | | When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL buildsAbel Vesa2019-02-151-4/+4
| | | | | | | | | Since the fsl_esdhc will also be used by SPL, make the preprocessor switches more generic to allow any kind of build. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imxTom Rini2019-01-301-0/+1
|\ | | | | | | For 2019.04
generated by cgit (git 2.34.1) at 2024-11-20 01:11:16 +0000