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* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-271-2/+2
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| * dm: Rename dev_get_parentdata() to dev_get_parent_priv()Simon Glass2015-10-231-2/+2
| | | | | | | | | | | | | | | | The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | allow LED initialization without STATUS_LED_BOOTBernhard Nortmann2015-10-242-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For current U-Boot to initialize status LEDs via status_led_init(), it is required to have both CONFIG_STATUS_LED and STATUS_LED_BOOT defined. This may be a particular concern with GPIO LEDs, where __led_init() is required to correctly set up the GPIO (gpio_request and gpio_direction_output). Without STATUS_LED_BOOT the initialization isn't called, which could leave the user with a non-functional "led" command - due to the fact that the LED routines in gpio_led.c use gpio_set_value() just fine, but the GPIO never got set up properly in the first place. I think having CONFIG_STATUS_LED is sufficient to justify a corresponding call to status_led_init(), even with no STATUS_LED_BOOT defined. To do so, common/board_r.c needs call that routine, so it now is exposed via status_led.h. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> [trini: Add dummy __led_init to pca9551_led.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | add generic stubs for GPIO LEDsBernhard Nortmann2015-10-231-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards that support LEDs driven via GPIO (CONFIG_GPIO_LED), it may be useful to have some generic stubs (wrapper functions) for the "colored" LEDs. This allows defining STATUS_LED_* values directly to GPIO numbers, e.g.: #define STATUS_LED_GREEN 248 /* = PH24 */ To keep those optional, it's probably best to introduce an additional configuration setting. I've chosen CONFIG_GPIO_LED_STUBS for that. Placing the code in drivers/misc/gpio_led.c also ensures that it automatically depends on CONFIG_GPIO_LED too. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | nios2: convert altera sysid to driver modelThomas Chou2015-10-233-0/+109
| | | | | | | | | | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: implement a Miscellaneous uclassThomas Chou2015-10-233-0/+61
|/ | | | | | | | | Implement a Miscellaneous uclass with generic read or write operations. This class is used only for those do not fit other more general classes. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: Correct operaion of 'reset' commandSimon Glass2015-10-051-1/+1
| | | | | | | | | | | | | | Currently 'reset' only works with the test device tree. When run without a device tree, or with the normal device tree, the following error is displayed: Reset not supported on this platform Fix the driver and the standard device tree to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* driver: misc: correct Kconfig entryPeng Fan2015-09-111-1/+1
| | | | | | | | | | | | | Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-022-6/+147
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| * mxc: ocotp fix hole in shadow registersPeng Fan2015-09-021-5/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: ocotp: mxc add i.MX7D supportAdrian Alonso2015-09-021-1/+73
| | | | | | | | | | | | | | | | | | * Ocotp of i.MX7D has different operation rule. This patch is to add support for i.MX7D ocotp. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * mxs_ocotp: Shift the HBUS divider correctlyChris Smith2015-09-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith <chris@zxdesign.info> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-012-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | driver: misc: debug server: Update Error messagePrabhakar Kushwaha2015-09-011-5/+5
|/ | | | | | | | Append "debug server FW" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-261-1/+12
| | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-121-0/+8
| | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* cros_ec: Remove the old tunnel codeSimon Glass2015-08-051-267/+1
| | | | | | This is not needed with driver mode. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Support the LDO access method used by springSimon Glass2015-08-051-10/+11
| | | | | | | | | | | | | | | | | | | | | | | Add a driver to support the special LDO access used by spring. This is a custom method in the cros_ec protocol - it does not use an I2C pass-through. There are two implementation choices: 1. Write a special LDO driver which can talk across the EC. Duplicate all the logic from TPS65090 for retrying when the LDO fails to come up. 2. Write a special I2C bus driver which pretends to be a TPS65090 and transfers reads and writes using the LDO message. Either is distasteful. The latter method is chosen since it results in less code duplication and a fairly simple (30-line) implementation of the core logic. The crosec 'ldo' subcommand could be removed (since i2c md/mw will work instead) but is retained as a convenience. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec: Convert the I2C tunnel code to use driver modelSimon Glass2015-08-051-5/+88
| | | | | | | | | | | | | | | | | | | The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This currently uses a copy of the I2C command code and a special 'crosec' sub-command. With driver model we can define an I2C bus which tunnels through to the EC, and use the normal 'i2c' command to access it. This simplifies the code and removes some duplication. Add an I2C driver which tunnels through to the EC. Adjust the EC code to support binding child devices so that it can be set up. Adjust the existing I2C xfer function to fit driver model better. For now the old code remains to allow things to still work. It will be removed in a later patch once the new flow is fully enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* misc: led: pca9551_led: Fix problem with multiple blink frequenciesStefan Roese2015-07-271-10/+22
| | | | | | | | | | | Only 2 frequencies are supported. The current driver implementation does not always use the 2 last configured blink frequencies. This patch fixes this problem. So that the last two entered frequencies are active. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tom Rini <trini@konsulko.com>
* dm: test: Add a test for the system controller uclassSimon Glass2015-07-212-0/+28
| | | | | | | Add a test to confirm that we can access system controllers and find their driver data. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Use the reset driver to handle resetSimon Glass2015-07-211-1/+1
| | | | | | | Move sandbox over to use the reset uclass for reset, instead of a direct call to do_reset(). This allows us to add tests. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add a warm and cold reset driverSimon Glass2015-07-212-0/+101
| | | | | | | | Add drivers for sandbox. One can only perform a warm reset (which does nothing). The other can perform a cold reset or a power reset (the latter will quit U-Boot). These can be used for testing the reset uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: reset: Allow reset_walk() to returnSimon Glass2015-07-211-6/+25
| | | | | | | | | | Add a new reset_walk_halt() function to cause a reset and then halt on failure. The reset_walk() function returns an error code. This is needed for testing since otherwise U-Boot will halt in the middle of a test. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add a system reset uclassSimon Glass2015-07-213-0/+72
| | | | | | | | | | | | | | | | It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver/fsl_debug_server: Fix the DDR hide logic for LS2085aBhupesh Sharma2015-07-201-0/+5
| | | | | | | | | | This patch fixes the DDR hide logic for LS2085a, correcting the way the Debug Server FW and MC FW images are placed on the top of system DDR and how the rest of the system DDR space is made visibile to Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* sandbox: cros_ec: Support EC_CMD_ENTERING_MODE emulationSimon Glass2015-05-141-0/+2
| | | | | | Emualate this function which is used with Chrome OS verified boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add missing errno.h includes in a few filesSimon Glass2015-05-142-0/+2
| | | | | | These files use error numbering, so add the include. Signed-off-by: Simon Glass <sjg@chromium.org>
* misc: led: Add PCA9551 LED driverStefan Roese2015-05-083-0/+169
| | | | | | | | | | This patch adds a driver for the PCA9551 LED controller. Originated-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Cc: Fabio Estevam <festevam@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* cros_ec: Handle the single duplex requirement in cros_ecSimon Glass2015-05-051-3/+20
| | | | | | | With several chips using the SPI protocol it seems better to put the single duplex functionality in the EC rather than the SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Show the protocol version in the debug messageSimon Glass2015-05-051-1/+2
| | | | | | | When starting up, show the protocol version that has been negotiated with the EC. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-291-1/+2
| | | | | | | | | For starting a Linux console on the superio serial port under interrupt mode, the IRQ number must be configured. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-243-0/+268
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| * armv8/ls2085aqds: NAND boot supportScott Wood2015-04-231-0/+12
| | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/fsl_ifc: Add support to finalize CS1, CS3 address bindingPrabhakar Kushwaha2015-04-231-0/+9
| | | | | | | | | | | | | | | | | | For fsl-lsch3, IFC is binded with address within 32-bit at fist. After u-boot relocates to DDR, CS1, CS3 can be binded to higher address to support large space. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-212-0/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | cmd_led: Extend led command to support blinking and more ledsStefan Roese2015-04-231-0/+14
|/ | | | | | | | | | | This patch extends the U-Boot "led" command to support automatic blinking by setting a blink frequency in milliseconds. Additionally the number of supported LEDs is increased to 6 (0...5). This will be used by the PCA9551 LED driver. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* sandbox: cros_ec: Add Kconfig for sandbox EC configSimon Glass2015-04-181-0/+9
| | | | | | Move CONFIG_CROS_EC_SANDBOX to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: exynos: Match up device tree with kernel versionSimon Glass2015-04-184-8/+8
| | | | | | | | | | | The U-Boot device trees are slightly different in a few places. Adjust them to remove most of the differences. Note that U-Boot does not support the concept of interrupts as distinct from GPIOs, so this difference remains. For sandbox, use the same keyboard file as for ARM boards and drop the host emulation bus which seems redundant. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Drop unused CONFIG_DM_CROS_ECSimon Glass2015-04-184-336/+0
| | | | | | | Since all supported boards enable this option now, we can remove it along with the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Reinit the cros_ec device when 'crosec init' is usedSimon Glass2015-04-181-2/+8
| | | | | | | This command is supposed to reinit the device. At present with driver model is does nothing. Implement this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec: Convert cros_ec LPC driver to driver modelSimon Glass2015-04-182-0/+50
| | | | | | | This is the last driver to be converted. It requires an LPC bus and a special check_version() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: pci: Enable PCI for sandboxSimon Glass2015-04-181-0/+1
| | | | | | | Enable PCI options so that sandbox can be used for testing this bus with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: Add a emulated PCI device as an exampleSimon Glass2015-04-181-0/+285
| | | | | | | | This device sits on the sandbox PCI bus and provides a case-swapping service for sandbox. It illustrates the use of both PCI I/O and PCI memory accesses. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add dev_get_uclass_priv() to access uclass private dataSimon Glass2015-04-164-7/+7
| | | | | | | | Add a convenience function to access the private data that a uclass stores for each of its devices. Convert over most existing uses for consistency and to provide an example for others. Signed-off-by: Simon Glass <sjg@chromium.org>
* fsl_sec_mon: Add driver for Security Monitor block of Freescalegaurav rana2015-03-053-0/+155
| | | | | | | | | | | | | The Security Monitor is the SOC’s central reporting point for security-relevant events such as the success or failure of boot software validation and the detection of potential security compromises. The API's for transition of Security states have been added which will be used in case of SECURE BOOT. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* dm: cros_ec: Convert to KconfigSimon Glass2015-02-191-1/+47
| | | | | | | | | Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Expand and complete Kconfig in drivers/Simon Glass2015-02-121-0/+9
| | | | | | | | Expand the help messages for each driver. Add missing Kconfig for I2C, SPI flash and thermal. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: cros_ec: Convert cros_ec_i2c over to driver modelSimon Glass2015-01-291-53/+29
| | | | | | | Move this driver to use driver model and update the snow configuration to match. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec_spi: Remove old pre-driver-model codeSimon Glass2015-01-291-49/+2
| | | | | | This is no-longer needed since all platforms use SPI for cros_ec. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-11-20 11:27:27 +0000