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* ddr: altera: sdram: Clean up set_sdr_static_cfg()Marek Vasut2015-08-081-8/+7
* ddr: altera: sdram: Clean up set_sdr_addr_rw()Marek Vasut2015-08-081-20/+10
* ddr: altera: sdram: Clean up set_sdr_dram_timing*()Marek Vasut2015-08-081-93/+53
* ddr: altera: sdram: Clean up set_sdr_ctrlcfg()Marek Vasut2015-08-081-38/+24
* ddr: altera: sdram: Clean up compute_errata_rows() part 2Marek Vasut2015-08-081-15/+20
* ddr: altera: sdram: Clean up compute_errata_rows() part 1Marek Vasut2015-08-081-7/+7
* ddr: altera: sdram: Switch to generic_hweight32()Marek Vasut2015-08-081-1/+1
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 5Marek Vasut2015-08-081-3/+5
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 4Marek Vasut2015-08-081-12/+5
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 3Marek Vasut2015-08-081-18/+6
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 2Marek Vasut2015-08-081-8/+10
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 1Marek Vasut2015-08-081-14/+13
* ddr: altera: Minor clean up of rw_mgr_mem_handoff()Marek Vasut2015-08-081-7/+8
* ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()Marek Vasut2015-08-081-22/+27
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()Marek Vasut2015-08-081-38/+21
* ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()Marek Vasut2015-08-081-13/+18
* ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3Marek Vasut2015-08-081-1/+11
* ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2Marek Vasut2015-08-081-39/+36
* ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1Marek Vasut2015-08-081-205/+201
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5Marek Vasut2015-08-081-1/+6
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4Marek Vasut2015-08-081-6/+7
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3Marek Vasut2015-08-081-3/+2
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2Marek Vasut2015-08-081-79/+88
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1Marek Vasut2015-08-081-61/+63
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11Marek Vasut2015-08-081-1/+10
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10Marek Vasut2015-08-081-4/+7
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9Marek Vasut2015-08-081-18/+17
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8Marek Vasut2015-08-081-18/+15
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7Marek Vasut2015-08-081-12/+9
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6Marek Vasut2015-08-081-89/+88
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5Marek Vasut2015-08-081-46/+44
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4Marek Vasut2015-08-081-17/+23
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3Marek Vasut2015-08-081-66/+60
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2Marek Vasut2015-08-081-170/+146
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1Marek Vasut2015-08-081-221/+197
* ddr: altera: Clean up rw_mgr_mem_calibrate_writes()Marek Vasut2015-08-081-12/+24
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5Marek Vasut2015-08-081-4/+13
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4Marek Vasut2015-08-081-9/+11
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3Marek Vasut2015-08-081-4/+3
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2Marek Vasut2015-08-081-15/+15
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1Marek Vasut2015-08-081-13/+16
* ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()Marek Vasut2015-08-081-15/+25
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7Marek Vasut2015-08-081-0/+6
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6Marek Vasut2015-08-081-17/+14
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5Marek Vasut2015-08-081-6/+6
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4Marek Vasut2015-08-081-54/+49
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3Marek Vasut2015-08-081-2/+3
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2Marek Vasut2015-08-081-10/+0
* ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1Marek Vasut2015-08-081-80/+70
* ddr: altera: Clean up find_vfifo_read()Marek Vasut2015-08-081-19/+18
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