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* clk: clk_set_default: accept no-op skip fieldsNeil Armstrong2018-08-041-0/+8
| | | | | | | | | | | | | | | The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135 Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: add clk_valid()Fabrice Gasnier2018-08-031-0/+13
| | | | | | | | | Add clk_valid() to check for optional clocks are valid. Call clk_valid() in test/dm/clk.c and add relevant test routine to sandbox clk tests. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32mp1: clk: support digital bypassPatrick Delaunay2018-07-201-9/+18
| | | | | | | | | HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: clk: add ADC clock gatingPatrick Delaunay2018-07-201-0/+7
| | | | | | | Add ADC clock gating, that may be used by STM32 ADC. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: clk: update Ethernet clock gatingPatrick Delaunay2018-07-201-2/+1
| | | | | | | Alignment with kernel clock driver Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: clk: add LDTC and DSI clock supportPatrick Delaunay2018-07-201-3/+93
| | | | | | | | | | | This patch add clk_enable/clk_disable/clk_get_rate support for - DSI_PX - LTDC_PX - DSI_K (only get rate) These clocks are needed for LTDC and DSI drivers with latest device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: clk: add common function pll_get_fvcoPatrick Delaunay2018-07-201-30/+61
| | | | | | | | | | the function compute the VCO PLL freq, used in - stm32mp1_read_pll_freq() - pll_set_rate() Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> # Conflicts: # drivers/clk/clk_stm32mp1.c
* stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macroPatrick Delaunay2018-07-201-9/+6
| | | | | | | | This patch define RCC_PLLNCFGR2_SHIFT to reuse it in the pll function for set rate. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* misc: stm32: Add STM32MP1 supportPatrick Delaunay2018-07-201-6/+0
| | | | | | | | | | | | Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* clk: zynqmp: Fixed the same if/else part error reported by coverityVipul Kumar2018-07-191-2/+4
| | | | | | | | This patch fixed the same if/else part error by adding the required source select on the basis of is_pre_src check. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clk: Add Actions Semi OWL clock supportManivannan Sadhasivam2018-07-095-0/+155
| | | | | | | | | This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: add Amlogic meson clock driverBeniamino Galvani2018-06-193-0/+441
| | | | | | | | Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: rmobile: Add R8A77995 RPC clockMarek Vasut2018-06-141-0/+5
| | | | | | | Add missing RPC entry into the R8A77995 clock driver tables. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* clk: rmobile: Add R8A77990 RPC clockMarek Vasut2018-06-141-0/+5
| | | | | | | Add missing RPC entry into the R8A77990 clock driver tables. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-06-025-32/+386
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| * clk: renesas: Add R8A77990 E3 clock tablesMarek Vasut2018-06-013-0/+311
| | | | | | | | | | | | | | Add clock tables for R8A77990 E3 SoC . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * clk: renesas: Add PE clock handlingMarek Vasut2018-06-012-6/+40
| | | | | | | | | | | | | | | | The PE clock have two parents, add support for picking the correct one and deriving the clock from it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * clk: renesas: Add PLL1 and PLL3 dividersMarek Vasut2018-06-011-4/+8
| | | | | | | | | | | | | | Add and use the PLL1 and PLL3 dividers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * clk: renesas: Pass clock rate around as 64bit number internallyMarek Vasut2018-06-011-25/+31
| | | | | | | | | | | | | | | | | | The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * clk: renesas: Fix swapped arguments in debug messageMarek Vasut2018-06-011-1/+1
| | | | | | | | | | | | | | | | The mul and div arguments were reported in reverse order in the debug message, swap them to fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | clk: bcm6345: convert to use live dtÁlvaro Fernández Rojas2018-06-011-6/+2
|/ | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* clk: at91: clk-h32mx: replace dm_warn with dev_dbgEugen Hristev2018-05-231-1/+1
| | | | | | | | dm_warn is too noisy, replace with dev_dbg for less noise. Based on original work by Wenyou Yang Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray2018-05-141-0/+10
| | | | | | | | | | | | | | | Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* clk: armada-37xx: Support soc_clk_dumpMarek Behún2018-05-142-1/+37
| | | | | | | | Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* driver: clk: Add support for clocks on Armada 37xxMarek Behún2018-05-146-0/+631
| | | | | | | | | | | | | | | | | | | | | | The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* clk: Add ICS8N3QV01 driverMario Six2018-05-083-0/+239
| | | | | | Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* clk: stm32mp1: Add VREF clock gatingFabrice Gasnier2018-05-081-0/+3
| | | | | | | Add VREF clock gating, that may be used by STM32 VREFBUF regulator. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* clk: clk_stm32f: Use PLLSAIP as USB 48MHz clockPatrice Chotard2018-05-081-11/+25
| | | | | | | | On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI output P can be used as 48MHz clock source for USB and SDMMC. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Tested By: Bruno Herrera <bruherrera@gmail.com>
* SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0754-107/+54
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* clk: renesas: Drop USB extal from the R8A7792 clock driverMarek Vasut2018-05-021-2/+0
| | | | | | | The R8A7792 does not have the USB extal, so drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-2715-30/+0
| | | | | | | | We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: rv1108: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+9
| | | | | | | | | | | | | Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
* rockchip: rk3128: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+10
| | | | | | | | | | | | | Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
* rockchip: rk3036: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+10
| | | | | | | | | | | | | Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSICWadim Egorov2018-04-251-0/+13
| | | | | | | | | | | | | | | The generic ehci-driver (ehci-generic.c) will try to enable the clocks listed in the DTSI. If this fails (e.g. due to clk_enable not being implemented in a driver and -ENOSYS being returned by the clk-uclass), the driver will bail our and print an error message. This implements a minimal clk_enable for the RK3288 and supports the clocks mandatory for the EHCI controllers; as these are enabled by default we simply return success. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* clk: uniphier: disable SPL_CLKMasahiro Yamada2018-04-241-1/+0
| | | | | | | The last clock consumer in SPL, SD/eMMC driver, gave up using the clock driver. The clock driver is only used in U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: renesas: Minor clean up of the R8A7794 clock driverMarek Vasut2018-04-211-7/+3
| | | | | | | | The initconst is not used in U-Boot, drop it. The r8a7794_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* clk: renesas: Minor clean up of the R8A7792 clock driverMarek Vasut2018-04-211-7/+3
| | | | | | | | The initconst is not used in U-Boot, drop it. The r8a7792_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge git://git.denx.de/u-boot-uniphierTom Rini2018-04-181-0/+6
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| * clk: uniphier: add ethernet clock control supportKunihiko Hayashi2018-04-181-0/+6
| | | | | | | | | | | | | | Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: fix clk_get_bulk when phandle errorNeil Armstrong2018-04-171-2/+2
|/ | | | | | | | This fixes the Coverity Defect CID 175347 when dev_count_phandle_with_args() returns a negative value. Fixes: a855be87da49 ("clk: Add get/enable/disable/release for a bulk of clocks") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: renesas: Minor clean up of the R8A7790 clock driverMarek Vasut2018-04-131-7/+3
| | | | | | | | The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* clk: add sandbox test for bulk APINeil Armstrong2018-04-101-0/+29
| | | | | | | | | | This patch adds the bulk clock API tests for the sandbox test suite. It's very similar to the main test but only uses the _bulk() API and checks if the clocks are correctly enabled/disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: Add get/enable/disable/release for a bulk of clocksNeil Armstrong2018-04-101-0/+59
| | | | | | | | | | | This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: zynqmp: Add new compatible string for clock driverMichal Simek2018-04-091-0/+1
| | | | | | New and old clk drivers are sharing IDs and descriptions. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clock: stm32mp1: add stgen clock source change supportPatrick Delaunay2018-04-061-1/+45
| | | | | | | | The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* rockchip: clk: rk3188: update dpll settings to make EMAC workAlexander Kochetkov2018-03-281-1/+1
| | | | | | | | | | | | | | | | | | The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dumpVipul Kumar2018-03-231-0/+75
| | | | | | | | This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clk: zynq: Show watchdog clock rate properlyMichal Simek2018-03-231-1/+1
| | | | | | | | | | | | | | watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-10-06 13:23:46 +0000