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* clk: stm32mp1: gets root clocks from fdtEtienne Carriere2021-03-111-39/+23
| | | | | | | | | | | | This change makes stm32mp1 clock driver to get the root clocks reference from the device node in the FDT rather than fetching straight these clocks by their name. Driver now stores the clock reference and use it to know if a root clock is present, get its rate or gets its related udevice reference. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini2021-02-233-0/+70
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
| * clk: versal: Add support to enable clocksT Karthik Reddy2021-02-231-0/+11
| | | | | | | | | | | | | | | | Add clock enable functionality in versal clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynqmp: Add support to enable clocksT Karthik Reddy2021-02-231-0/+49
| | | | | | | | | | | | | | | | Add clock enable functionality in zynqmp clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynq: Add dummy clock enable functionMichal Simek2021-02-231-0/+10
| | | | | | | | | | | | | | | | | | A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | clk: ti: improve debug messages for clkctrl driverDario Binacchi2021-02-221-2/+2
| | | | | | | | | | | | | | | | | | The previous version printed the same debug message for both the enable and disable routines without highlighting whether you were enabling or disabling the module. It is now clear whether you are enabling or disabling the module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1520-2/+20
|\ \ | | | | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * | common: Drop asm/global_data.h from common headerSimon Glass2021-02-0220-2/+20
| |/ | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | clk: at91: compat: partially revert "dm: Remove uses of device_bind_offset()"Eugen Hristev2021-02-111-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert changes in at91 compat.c that cause u-boot to fail booting on sama5d4_xplained and sama5d2_xplained Log below: <debug_uart> No serial driver found Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Fixes: a2703ce10c ("dm: Remove uses of device_bind_offset()") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clk: stm32mp1: add support of I2C6_KPatrick Delaunay2021-02-091-0/+1
|/ | | | | | | | | | | Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR = I2C6EN: I2C6 peripheral clocks enable. This patch allows customer to use I2C6 in SPL or in U-Boot as other I2C instance, already support in clk driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* clk: x86: Correct the driver nameSimon Glass2021-01-301-2/+2
| | | | | | | The current driver name does not match its compatible string, so of-platdata does not work correctly. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* clk: Add debugging for return valuesSimon Glass2021-01-301-5/+11
| | | | | | | Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-01-253-0/+128
|\ | | | | | | | | | | | | | | - New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
| * clk: sunxi: Add support for H616 clocksJernej Skrabec2021-01-253-0/+128
| | | | | | | | | | | | | | | | This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2021-01-252-0/+160
|\ \ | |/ |/| | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
| * clk: add clock driver for MediaTek MT7620 SoCWeijie Gao2021-01-242-0/+160
| | | | | | | | | | | | | | | | | | This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | clk: imx: Add ECSPI to iMX8MNMarek Vasut2021-01-231-0/+29
|/ | | | | | | | | | | Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* clk: aspeed: Add AST2600 clock supportRyan Chen2021-01-182-0/+1174
| | | | | | | | This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
* clk: mediatek: Add MT8183 clock driverFabien Parent2021-01-182-0/+824
| | | | | | | Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* clk: Add Microchip PolarFire SoC clock driverPadmarao Begari2021-01-188-0/+514
| | | | | | | | | Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* dm: fix build errors generated by last mergesDario Binacchi2021-01-155-5/+5
| | | | | | | | | | | | | | | Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
* Merge tag 'u-boot-stm32-20210113' of ↵Tom Rini2021-01-133-127/+129
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Enable logging features for stm32mp15 boards - Update MAINTAINERS emails for STI and STM32 - Activate OF_LIVE for ST stm32mp15 boards - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards - Correction in stm32prog command on uart: always flush DFU on start command - Update USB-C power detection algorithm on DK boards
| * clk: clk_stm32h7: migrate trace to dev and log macroPatrick Delaunay2021-01-131-32/+38
| | | | | | | | | | | | | | | | | | | | Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * clk: clk_stm32f: migrate trace to dev and log macroPatrick Delaunay2021-01-131-19/+20
| | | | | | | | | | | | | | | | | | | | Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * clk: stm32mp1: migrate trace to dev and log macroPatrick Delaunay2021-01-131-76/+71
| | | | | | | | | | | | | | | | | | | | Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini2021-01-132-0/+84
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
| * clk: meson: add minimal driver for g12a-ao clocksMarek Szyprowski2021-01-112-0/+84
| | | | | | | | | | | | | | | | | | | | | | Add minimal driver AO clocks on meson G12A family. Only ADC related clocks are supported. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | clk: move clk-ti-sci driver to 'ti' directoryDario Binacchi2021-01-125-9/+9
| | | | | | | | | | | | | | The patch moves the clk-ti-sci.c file to the 'ti' directory along with all the other TI's drivers, and renames it clk-sci.c. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: omap4: add clock manager driverDario Binacchi2021-01-122-1/+23
| | | | | | | | | | | | | | | | | | This minimal driver is only used to bind child devices. For DT binding details see Linux doc: - Documentation/devicetree/bindings/arm/omap/prcm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add support for clkctrl clocksDario Binacchi2021-01-123-0/+161
| | | | | | | | | | | | | | | | | | | | | | Until now the clkctrl clocks have been enabled/disabled through platform routines. Thanks to this patch they can be enabled and configured directly by the probed devices that need to use them. For DT binding details see Linux doc: - Documentation/devicetree/bindings/clock/ti-clkctrl.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add gate clock driverDario Binacchi2021-01-123-0/+100
| | | | | | | | | | | | | | | | | | The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add divider clock driverDario Binacchi2021-01-126-25/+439
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: am33xx: add DPLL clock driversDario Binacchi2021-01-124-0/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: ti: add mux clock driverDario Binacchi2021-01-125-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | clk: add clk_round_rate()Dario Binacchi2021-01-123-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | clk: export generic routinesDario Binacchi2021-01-121-12/+12
| | | | | | | | | | | | | | | | Export routines that can be used by other drivers avoiding duplicating code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-0522-25/+38
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * | dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-055-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Access device ofnode through functionsSimon Glass2021-01-053-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | dm: core: Access device flags through functionsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | At present flags are stored as part of the device. In preparation for storing them separately, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Use access methods for dev/uclass private dataSimon Glass2021-01-0513-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* | | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-053-5/+26
|\ \ \ | |/ / |/| / | |/ | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵Tom Rini2020-12-111-4/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
| | * clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypassClaudiu Beznea2020-12-071-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini2020-12-091-1/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
| | * | treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2020-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | imx: clk: added IPG Clock for I2C on imx8qmOliver Graute2020-12-061-0/+24
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes this clk issue on I2C on imx8qm => i2c bus Bus 3: i2c@5a830000 => i2c dev 3 Setting bus to 3 Failed to enable ipg clk Failure changing bus number (-524) Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | | dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-133-59/+59
| | | | | | | | | | | | | | | | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-1318-44/+44
| | | | | | | | | | | | | | | | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-06-28 05:24:24 +0000