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* clk: Update drivers to use -EINVALSimon Glass2021-04-064-9/+9
| | | | | | | | | | | At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* clk: imx: Add ECSPI to iMX8MNMarek Vasut2021-01-231-0/+29
| | | | | | | | | | | Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-051-1/+1
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
* | imx: clk: added IPG Clock for I2C on imx8qmOliver Graute2020-12-061-0/+24
|/ | | | | | | | | | | | | | | | | This patch fixes this clk issue on I2C on imx8qm => i2c bus Bus 3: i2c@5a830000 => i2c dev 3 Setting bus to 3 Failed to enable ipg clk Failure changing bus number (-524) Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clockLukasz Majewski2020-08-241-0/+7
| | | | | | | | | | | | | | After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide PTP clock. On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux kernel's CCF. Code in this change models the simplest case when enet reference clock is generated from 'osc' clock. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: Add support for pllv3 enet clockLukasz Majewski2020-08-241-0/+25
| | | | | | | | | | This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* clk: imx6: Add definition for IMX6QDL_CLK_ENET clockLukasz Majewski2020-08-241-0/+1
| | | | | | | | | | After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide IMX6QDL_CLK_ENET. This change defines the missing clock in i.MX6Q's CCF. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* clk: imx8m: drop clk settingsPeng Fan2020-07-142-68/+0
| | | | | | | We use non-dm code to configure the clk settings in order to simplify dm clk driver in future, so remove the duplicated code from clk driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx8mp: Update imx8mp ccf clock driverYe Li2020-07-141-0/+52
| | | | | | | | Add clocks for FEC and flexspi, and add set parent clock callback, so DTS can assign clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx8mm/8mn: Add USB clocksYe Li2020-07-142-0/+37
| | | | | | | | Add USB relevant clocks to support usb clock settings for both DM USB host and gadget drivers Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: clk-imx8mn: Update clock tree and support set parentYe Li2020-07-141-0/+56
| | | | | | | | Add set clock parent support. Add ENET and flexspi related clocks to support assigned clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx8mm: Add qspi clockPeng Fan2020-07-141-0/+7
| | | | | | Add qspi clock Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx8mm: fix clk set parentPeng Fan2020-07-141-1/+4
| | | | | | | Fix clk set parent, so we could still have correct clocks after parent changing. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* dm: Fix error handling for dev_read_addr_ptrSean Anderson2020-07-011-1/+1
| | | | | | | | | | | | dev_read_addr_ptr had different semantics depending on whether OF_LIVE was enabled. This patch converts both implementations to return NULL on error, and converts all call sites which check for FDT_ADDR_T_NONE to check for NULL instead. This patch also removes the call to map_physmem, since we have dev_remap_addr* for those semantics. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: Always use the supplied struct clkSean Anderson2020-07-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite clock did not have the ->dev field filled in. This was fine, because the device-specific clock information would be used. However, since there was no ->dev, there was no way to get the parent clock. This caused the recalc_rate method of the CCF divider clock to fail. One option would be to use the clk->priv field to get the composite clock and from there get the appropriate parent device. However, this would tie the implementation to the composite clock. In general, different devices should not rely on the contents of ->priv from another device. The simple solution to this problem is to just always use the supplied struct clock. The composite clock now fills in the ->dev pointer of its child clocks. This allows child clocks to make calls like clk_get_parent() without issue. imx avoided the above problem by using a custom get_rate function with composite clocks. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-189-0/+9
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* clk: imx: clk-imxrt1050: fix lcdif clock gateGiulio Benetti2020-05-011-1/+1
| | | | | | | | LCDIF clock gate was wrong so set it according to RM. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* clk: imx: add i.IMXRT1020 clk driverGiulio Benetti2020-04-183-0/+244
| | | | | | | Add i.MXRT1020 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: clk-imxrt1050: add set_parent() callbackGiulio Benetti2020-04-181-0/+19
| | | | | | | Need to add set_parent() callback to allow dts assigned-clock-parents to work so let's add it accordingly. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPLGiulio Benetti2020-04-181-1/+8
| | | | | | | | mxsfb needs PLL5 as source, so let's setup it at its default frequency specified in RM(650Mhz). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: clk-imxrt1050: fix typo in clock name "video:"Giulio Benetti2020-04-181-1/+1
| | | | | | | "video:" must be "video", ":" is a typo. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add enable_bitGiulio Benetti2020-04-181-0/+9
| | | | | | | | | pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-051-0/+1
| | | | | | | | | | | | At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Require users of devres to include the headerSimon Glass2020-02-055-0/+10
| | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti2020-01-261-0/+3
| | | | | | | | Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: Fix error checking of dev_read_addr_ptrSean Anderson2020-01-263-3/+3
| | | | | | dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: imx: add i.IMXRT1050 clk driverGiulio Benetti2020-01-143-0/+310
| | | | | | Add i.MXRT1050 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pfd: add set_rate()Giulio Benetti2020-01-141-0/+22
| | | | | | | Implement set_rate() for pfd. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti2020-01-141-0/+76
| | | | | | Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti2020-01-141-0/+53
| | | | | | | | | Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add set_rate() supportGiulio Benetti2020-01-141-0/+27
| | | | | | | Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add disable() supportGiulio Benetti2020-01-141-0/+16
| | | | | | | Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add enable() supportGiulio Benetti2020-01-141-0/+24
| | | | | | | | | Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti2020-01-141-0/+2
| | | | | | | div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti2020-01-141-5/+15
| | | | | | | | | Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin2020-01-141-0/+12
| | | | | | | | | | Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* clk: imx: add i.MX8MP clk driverPeng Fan2020-01-083-0/+380
| | | | | | Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx: add imx_clk_mux2_flagsPeng Fan2020-01-081-0/+10
| | | | | | Add imx_clk_mux2_flags which will be used by i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]Frieder Schrempf2019-12-061-1/+1
| | | | | | | | The 24MHz oscillator clock is referenced by "clock-osc-24m" and not "osc_24m". Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* clk: imx: imx8mm: add set_parent callbackPeng Fan2019-11-051-0/+19
| | | | | | | | | Add set_parent callback, then assigned-clock-parents in dts could be work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
* clk: imx8mm: add enet clkPeng Fan2019-11-051-0/+27
| | | | | | | | | Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
* clk: imx: add i.MX8MN ccf driverPeng Fan2019-11-053-0/+433
| | | | | | | | | Add i.MX8MM ccf driver support. Modifed from Linux Kernel 5.3.0-rc1, drop some entries that not used in U-Boot and adapt to U-Boot CCF style. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Lukasz Majewski <lukma@denx.de>
* clk: Add support for I2C clocks on NXP's imx6q SoC which use CCFLukasz Majewski2019-10-222-0/+39
| | | | | | | | | | This change adds support for I2C clock modeled in CCF. This code intention is to only enable those clocks in the I2C driver with default settings. For that reason the "busy" versions of clocks reuse the generic approach and would need to be updated when one wants to adjust the I2C clock frequency in U-Boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: add i.MX8MM clk driverPeng Fan2019-08-222-0/+417
| | | | | | Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: imx: add i.MX8M composite clk supportPeng Fan2019-08-221-0/+170
| | | | | | Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2024-11-15 19:05:06 +0000