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* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-06-041-0/+1
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| * phy: Add Allwinner A64 USB PHY driverJagan Teki2018-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB PHY implementation for Allwinner SOC's can be handling in to single driver with different phy configs. This driver handle all Allwinner USB PHY's start from 4I to 50I(except 9I). Currently added A64 compatibility more will add in next coming patches. Current implementation is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future. Driver named as phy-sun4i-usb.c since the same PHY logic work for all Allwinner SOC's start from 4I to A64 except 9I with different phy configurations. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
* | fastboot: Extract fastboot_okay/fail to fb_common.cAlex Kiernan2018-05-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add drivers/fastboot/fb_common.c, where fastboot_okay/fail are implemented so we can call them from a non-USB implementation. Introduce fastboot_response which takes varargs parameters so we can use it to generate formatted response strings. Refactor fastboot_okay/fail to use it. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | fastboot: Move fastboot to drivers/fastbootAlex Kiernan2018-05-301-0/+3
|/ | | | | | | | | | | | | | Separate CMD_FASTBOOT from FASTBOOT and move code and configuration to drivers/fastboot. Switch dependencies on FASTBOOT to USB_FUNCTION_FASTBOOT as anyone who wants FASTBOOT before this series wants USB_FUNCTION_FASTBOOT. Split USB_FUNCTION_FASTBOOT from FASTBOOT so they retain their existing behaviour. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* bootcount: spl: Enable bootcount support in SPLLukasz Majewski2018-05-101-0/+1
| | | | | | | | | | | | | New, SPL related config option - CONFIG_SPL_BOOTCOUNT_LIMIT has been added to allow drivers/bootcount code re-usage in SPL. This code is necessary to use and setup bootcount in SPL in the case of falcon boot mode. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-3/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: add SPL_RESET_SUPPORTPatrick Delaunay2018-03-191-0/+1
| | | | | | | | Add option to include RESET driver and uclass in SPL. That can be useful to handle IP reset with same driver in U-Boot and in SPL. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* spl: Kconfig: Rename SPL_USBETH_SUPPORT to SPL_USB_ETHER to match with the ↵Faiz Abbas2018-03-051-1/+1
| | | | | | | | | | | U-boot CONFIG Rename CONFIG_SPL_USBETH_SUPPORT to CONFIG_SPL_USB_ETHER. This enables users to block text using CONFIG_IS_ENABLED() instead of resorting to #if ladders with SPL and non-SPL cases. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* thermal: ti-bandgap: Add support for temperature sensorFaiz Abbas2017-11-211-0/+1
| | | | | | | | | | The dra7xx series of SOCs contain a temperature sensor and an associated analog-to-digital converter (ADC) which produces an output which is proportional to the SOC temperature. Add support for this temperature sensor. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini2017-08-141-22/+17
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| * dm: timer: normalise SPL and TPL supportPhilipp Tomsich2017-08-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * drivers: spl: consistently use the $(SPL_TPL_) macroPhilipp Tomsich2017-08-131-20/+16
| | | | | | | | | | | | | | | | | | | | | | | | To simplify drivers/Makefile a bit when using TPL/SPL, we consistently use the $(SPL_TPL_) macro to test for drivers that have separate configuration symbols for the full U-boot, SPL and TPL stages. Instead of explicitly repeating them in two separate if-guarded sections of the Makefile, we can now simply list these options once. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | nvme: Add NVM Express driver supportZhikang Zhang2017-08-131-0/+1
|/ | | | | | | | | | | | | | | | | | | | NVM Express (NVMe) is a register level interface that allows host software to communicate with a non-volatile memory subsystem. This interface is optimized for enterprise and client solid state drives, typically attached to the PCI express interface. This adds a U-Boot driver support of devices that follow the NVMe standard [1] and supports basic read/write operations. Tested with a 400GB Intel SSD 750 series NVMe card with controller id 8086:0953. [1] http://www.nvmexpress.org/resources/specifications/ Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com> Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: Enable FPGA driver build on SPLTien Fong Chee2017-07-261-0/+1
| | | | | | | | | | Enable FPGA driver build for Arria 10 SPL because FPGA driver is needed by Arria 10 SPL to configure and getting DDR up before loading U-boot into DDR and booting from there. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
* scsi: Move drivers into new drivers/scsi directorySimon Glass2017-07-111-1/+2
| | | | | | | | | At present we have the SCSI drivers in the drivers/block and common/ directories. It is better to split them out into their own place. Use drivers/scsi which is what Linux does. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sata: Move drivers into new drivers/ata directorySimon Glass2017-07-111-1/+2
| | | | | | | | | At present we have the SATA and PATA drivers mixed up in the drivers/block directory. It is better to split them out into their own place. Use drivers/ata which is what Linux does. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Drop digital thermometer and thermostat (DTT) driversSimon Glass2017-05-221-1/+0
| | | | | | | | | | This subsystem is quite old. It has been replaced with a driver-model version (UCLASS_THERMAL). Boards are free to convert to that if required, but here is a removal patch that could be applied in the meantime. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* Drop three-wire serial (TWS) supportSimon Glass2017-05-221-1/+0
| | | | | | | | | | This subsystem has not been converted to driver model, there is only one driver and only one board that uses it. Drop it and its CONFIG option. Also drop the rtc4543 RTC driver since it uses TWS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: descend into drivers/mmc only when CONFIG_MMC is enabledMasahiro Yamada2017-05-151-0/+1
| | | | | | | | This simplifies makefiles. Also, arrange the order of objects in drivers/mmc/Makefile so that the framework objects are listed before drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* drivers: phy: add generic PHY frameworkJean-Jacques Hiblot2017-05-091-0/+1
| | | | | | | | | | | The PHY framework provides a set of APIs to control a PHY. This API is derived from the linux version of the generic PHY framework. Currently the API supports init(), deinit(), power_on, power_off() and reset(). The framework provides a way to get a reference to a phy from the device-tree. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sysreset: psci: support system reset in a generic way with PSCIMasahiro Yamada2017-04-181-2/+3
| | | | | | | | | | | | | | | If the system is running PSCI firmware, the System Reset function (func ID: 0x80000009) is supposed to be handled by PSCI, that is, the SoC/board specific reset implementation should be moved to PSCI. U-Boot should call the PSCI service according to the arm-smccc manner. The arm-smccc is supported on ARMv7 or later. Especially, ARMv8 generation SoCs are likely to run ARM Trusted Firmware BL31. In this case, U-Boot is a non-secure world boot loader, so it should not be able to reset the system directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dm: core: Allow driver model to be disabled for TPLSimon Glass2017-04-051-1/+1
| | | | | | | | | Since TPL often needs to be very very small it may not make sense to enable driver model. Add an option for this. This changes brings the 'rock' board under the TPL limit with gcc 4.9. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: Allow PCH drivers to be used in SPLSimon Glass2017-02-061-0/+1
| | | | | | | Add an option for building Platorm Controller Hub drivers in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow timer drivers to be used in SPLSimon Glass2017-02-061-0/+1
| | | | | | | Add a new Kconfig option to allow timer drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow RTC drivers to be used in SPLSimon Glass2017-02-061-0/+1
| | | | | | | Add a new Kconfig option to allow RTC drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow PCI drivers to be used in SPLSimon Glass2017-02-061-0/+1
| | | | | | | Add a new Kconfig option to allow PCI drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow CPU drivers to be used in SPLSimon Glass2017-02-061-0/+1
| | | | | | | Add a new Kconfig option to allow CPU drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: add USB Gadget config optionStefan Agner2016-11-281-3/+2
| | | | | | | | | Introduce USB Gadget config option. This allows to combine Makefile entries for SPL_USBETH_SUPPORT and SPL_DFU_SUPPORT. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Ravi Babu <ravibabu@ti.com>
* spl: dfu: move DFU Kconfig to SPL KconfigStefan Agner2016-11-281-0/+3
| | | | | | | | | | | | | | | | The DFU Kconfig menu entries should be part of the SPL Kconfig file. Also avoid using the top level Makefile by moving the config dependent build artifacts to the driver/ and driver/usb/gadget/ Makfiles. With that, DFU can be built again in SPL if CONFIG_SPL_DFU_SUPPORT is enabled. Fixes: 6ad6102246d8 ("usb:gadget: Disallow DFU in SPL for now") Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3kStefan Roese2016-09-271-0/+1
| | | | | | | | | | | | | | | | | | This version is based on the Marvell U-Boot version with this patch applied as latest patch: Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb device mode" from 2016-07-05. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* Use separate options for TPL supportSimon Glass2016-09-161-1/+15
| | | | | | | | | | | | | | | At present TPL uses the same options as SPL support. In a few cases the board config enables or disables the SPL options depending on whether CONFIG_TPL_BUILD is defined. With the move to Kconfig, options are determined for the whole build and (without a hack like an #undef in a header file) cannot be controlled in this way. Create new TPL options for these and update users. This will allow Kconfig conversion to proceed for these boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers/sysreset: group sysreset driversMax Filippov2016-08-121-1/+2
| | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mtd: Sort subsystem directories aplhabeticaly in MakefileLadislav Michl2016-07-221-2/+2
| | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Add a reset driver framework/uclassStephen Warren2016-06-191-0/+1
| | | | | | | | | | | | | | | | A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* verified-boot: Minimal support for booting U-Boot proper from SPLTeddy Reed2016-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a board to configure verified boot within the SPL using a FIT or FIT with external data. It also allows the SPL to perform signature verification without needing relocation. The board configuration will need to add the following feature defines: CONFIG_SPL_CRYPTO_SUPPORT CONFIG_SPL_HASH_SUPPORT CONFIG_SPL_SHA256 In this example, SHA256 is the only selected hashing algorithm. And the following booleans: CONFIG_SPL=y CONFIG_SPL_DM=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_FIT_SIGNATURE=y Signed-off-by: Teddy Reed <teddy.reed@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Sumit Garg <sumit.garg@nxp.com>
* Add a mailbox driver framework/uclassStephen Warren2016-05-261-0/+1
| | | | | | | | | | | | | | | | A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: mmc: spl: Use the legacy block interface in SPLSimon Glass2016-05-171-0/+1
| | | | | | | Bring this in for SPL so that we can use generic code for loading from block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: usb: Drop the get_dev() functionSimon Glass2016-05-171-0/+1
| | | | | | This function is implemented by the legacy block functions now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-011-0/+1
| | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-011-0/+1
| | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Expand the uclass for Platform Controller Hubs (PCH)Simon Glass2016-01-241-0/+1
| | | | | | | | | | | | | | A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: mvebu: Move SoC selection (A38X vs AXP) into KconfigStefan Roese2016-01-141-2/+2
| | | | | | | | | | | | | | | | | | Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-101-0/+4
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: implement a Timer uclassThomas Chou2015-10-231-0/+1
| | | | | | | Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: Introduce a simplified remoteproc frameworkNishanth Menon2015-10-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* pinctrl: add pin control uclass supportMasahiro Yamada2015-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* led: unify obj-$(CONFIG_LED) and obj-$(CONFIG_SPL_LED) entriesMasahiro Yamada2015-08-181-2/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* led: rename CONFIG_SPL_LED_SUPPORT to CONFIG_SPL_LEDMasahiro Yamada2015-08-181-1/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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