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* dm: reset: add stm32 reset driverPatrice Chotard2017-09-221-0/+6
| | | | | | | | | | | | | | | | | This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard2017-09-221-0/+152
| | | | | | | | | | | | | | | | | | This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: dwc3: Add dwc3 glue driver support for STiPatrice Chotard2017-09-221-0/+60
| | | | | | | | | | | | This patch adds the ST glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Part of this code been extracted from kernel.org driver (drivers/usb/dwc3/dwc3-st.c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: phy: Add STi USB2 PHYPatrice Chotard2017-09-221-0/+24
| | | | | | | | | This is the generic phy driver for the picoPHY ports used by USB2/1.1 controllers. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: add i2c driver for stm32Patrice Chotard2017-08-231-0/+30
| | | | | | | | | | | | | | | | | | | | | | Add i2c driver which can be used on both STM32F7 and STM32H7. This I2C block supports the following features: _ Slave and master modes _ Multimaster capability _ Standard-mode (up to 100 kHz) _ Fast-mode (up to 400 kHz) _ Fast-mode Plus (up to 1 MHz) _ 7-bit and 10-bit addressing mode _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) _ All 7-bit addresses acknowledge mode _ General call _ Programmable setup and hold times _ Easy to use event management _ Optional clock stretching _ Software reset Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3368: add DRAM controller driver with DRAM initialisationPhilipp Tomsich2017-08-131-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: stm32: add second SDRAM bank managementPatrice Chotard2017-07-261-6/+13
| | | | | | | | | | | FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integerBin Meng2017-06-051-6/+6
| | | | | | | | | | | | At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Use macros instead of magic numbers for FSP settingsBin Meng2017-06-051-52/+22
| | | | | | | | | Introduce various meaningful macros for FSP settings and switch over to use them instead of magic numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Remove "serial-debug-port-*" settingsBin Meng2017-06-051-2/+0
| | | | | | | | | "serial-debug-port-address" and "serial-debug-port-type" settings are actually reserved in the FSP UPD data structure. Remove them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redundPhilipp Tomsich2017-05-291-0/+12
| | | | | | | | | | Adding documentation on the new config properties: 'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET 'u-boot,mmc-env-offset-redundant' - overrides CONFIG_ENV_OFFSET_REDUND Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* doc: document /config/u-boot, spl-payload-offset propertyPhilipp Tomsich2017-05-111-0/+5
| | | | | | | | | This adds documentation on the u-boot,spl-payload-offset property (which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in the SPL stage, if present). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-05-101-0/+69
|\ | | | | | | | | | | This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
| * doc: dtbinding: add pwm binding fileKever Yang2017-05-101-0/+69
| | | | | | | | | | | | | | This is a copy from kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: led: add BCM6358 led driverÁlvaro Fernández Rojas2017-05-101-0/+141
| | | | | | | | | | | | | | This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: led: add BCM6328 led driverÁlvaro Fernández Rojas2017-05-101-0/+106
|/ | | | | | | | This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c, simplified to remove HW leds and blink fallbacks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DT: stm32f7: add sdram pin contol nodeVikas Manocha2017-05-081-0/+51
| | | | | | | Also added DT binding doc for stm32 fmc(flexible memory controller). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
* at91: video: DT binding for HLCDC driverSongjun Wu2017-04-141-0/+42
| | | | | | DT binding documentation for atmel HLCDC driver. Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
* rockchip: rk3399: spl: make SPL boot-order configurable via /chosenPhilipp Tomsich2017-04-041-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399 does not have any boot selection pins and the BootROM probes the boot interfaces using the following boot-order: 1. SPI 2. eMMC (sdhci in DTS) 3. SD card (sdmmc in DTS) 4. USB loader For ease of deployment, the SPL stage should mirror the boot order of the ROM and use the same probing order (assuming that valid images can be detected by SPL) unless instructed otherwise. The boot-order can then be configured via the 'u-boot,spl-boot-order' property in the chosen-node of the DTS. While this approach is easily extensible to other boards, it is only implemented for the RK3399 for now, as the large SRAM on the RK3399 makes this easy to fit the needed infrastructure into SPL and our production setup already runs with DM, OF_CONTROL and BLK in SPL. The new boot-order property is expected to be used in conjunction with FIT images (and all legacy image formats disabled via Kconfig). A boot-sequence with probing and fallthroughs from SPI via eMMC to SD card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers/net/phy: add fixed-phy / fixed-link supportHannes Schmelzer2017-03-261-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for having a "fixed-link" to some other MAC (like some embedded switch-device). For this purpose we introduce a new phy-driver, called "Fixed PHY". Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is described with a subnode below ethernet interface. Most ethernet drivers (unfortunately not all are following same scheme for searching/attaching phys) are calling "phy_connect(...)" for getting a phy-device. At this point we link in, we search here for a subnode called "fixed- link", once found we start phy_device_create(...) with the special phy- id PHY_FIXED_ID (0xa5a55a5a). During init the "Fixed PHY" driver has registered with this id and now gets probed, during probe we get all the details about fixed-link out of dts, later on the phy reports this values. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* Merge git://git.denx.de/u-boot-arcTom Rini2017-03-241-0/+24
|\ | | | | | | | | | | | | This replaces legacy arch/arc/lib/timer.c implementation and allows us to describe ARC Timers in Device Tree. Among other things that way we may properly inherit Timer's clock from CPU's clock s they really run synchronously.
| * drivers: timer: Introduce ARC timer driverVlad Zakharov2017-03-241-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mvebu: usb: xhci: Add VBUS regulator supply to the host driverKonstantin Porotchkin2017-03-231-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB device should linked to VBUS regulator through "vbus-supply" DTS property. This patch adds handling for "vbus-supply" property inside the USB device entry for turning on the VBUS regulator upon the host adapter probe. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | mvebu: pcie: Add support for GPIO reset for PCIe deviceKonstantin Porotchkin2017-03-231-0/+49
|/ | | | | | | | | | | | | | | | Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* part_efi: document device-tree binding for part_efi configurationPhilipp Tomsich2017-03-201-0/+8
| | | | | | | | | This adds documentation on the u-boot,efi-partition-entries-offset property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if present). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: move documentation for /config node into a separate filePhilipp Tomsich2017-03-201-0/+14
| | | | | | | | This moves the description of the /config node from README.fdt-control into a separate file doc/device-tree-bindings/config.txt. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-03-171-0/+42
|\ | | | | | | | | | | This includes support for rk3188 from Heiko Stübner and and rk3328 from Kever Yang. Also included is SPL support for rk3399 and a fix for rk3288 to get it booting again (spl_early_init()).
| * rockchip: arm64: rk3399: add ddr controller driverKever Yang2017-03-161-0/+42
| | | | | | | | | | | | | | | | | | RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from coreboot, support 4GB lpddr3 in this version. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
* | PINCTRL: stm32f7: add pin control driverVikas Manocha2017-03-171-0/+133
| | | | | | | | | | | | | | | | | | This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clk: stm32f7: add clock driver for stm32f7 familyVikas Manocha2017-03-171-0/+95
|/ | | | | | | | add basic clock driver support for stm32f7 to enable clocks required by the peripherals. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DTS: stm32: add stm32f746-disco device tree filesMichael Kurz2017-01-281-0/+39
| | | | | | | | | | | This patch adds the DTS source files needed for stm32f746-disco board The files are based on the stm32f429/469 files from current linux kernel. Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi" Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* regulator: fixed: Add support to handle enable-active-high DT propertyVignesh R2016-12-271-0/+4
| | | | | | | | | Add support to handle enable-active-high DT property. This property is used to drive the gpio controlling fixed regulator as active high when claiming gpio line. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* arm64: mvebu: Add pin control nodes to A8K family DTS filesKonstantin Porotchkin2016-12-121-22/+22
| | | | | | | | | | | | | | | Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-123-0/+408
| | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* serial: pl01x: expose skip_init platdata option in DTFabian Vogt2016-11-281-0/+3
| | | | | | | | | To be able to represent the skip-init platdata element with OF_CONTROL, it needs to be read from the device tree as well and put into the platform data. Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* serial: bcm283x_mu: add device tree supportFabian Vogt2016-11-281-0/+10
| | | | | | | This patch adds device tree support for the bcm283x mini-uart driver. Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: bcm2835: add device tree supportFabian Vogt2016-11-281-0/+5
| | | | | | | This patch adds device tree support for the bcm2835 GPIO driver. Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Rename sf_params.c to spi_flash_ids.cJagan Teki2016-11-181-1/+1
| | | | | | | | | | | | | | | Now the flash params table as renamed to spi_flash_ids structure, so rename the sf_params.c to spi_flash_ids.c and remove the legacy. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* dt: net: add DWC EQoS bindingStephen Warren2016-11-071-0/+166
| | | | | | | | | | | | | | | The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which supports multiple options for bus type, clocking and reset structure, and feature list. This patch imports the binding from the Linux kernel, including my V3 patch to extend the binding to cover the Tegra186, which is applied for next-20160912. So far, my changes have been acked by Lars Persson, the original author of the binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* power: pmic: add Ricoh RN5T567 PMIC supportStefan Agner2016-10-071-0/+17
| | | | | | | | Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: imx: serial: support device treeStefan Agner2016-10-071-0/+8
| | | | | | | | Support instatiation through device tree. Also parse the fsl,dte-mode property to determine whether DTE mode shall be used. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* regulator: fixed: obey startup delayJohn Keeping2016-09-061-0/+1
| | | | | | | | | | When enabling a fixed regulator, it may take some time to rise to the correct voltage. If we do not delay here then subsequent operations will fail. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* atmel: Bring in at91 pio4 device tree file and bindingsWenyou Yang2016-08-151-0/+66
| | | | | | | | Bring in required device tree file and bindings from Linux. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: atmel: DT binding for i2c driverSongjun Wu2016-08-151-0/+26
| | | | | | | | DT binding documentation for atmel i2c driver. Signed-off-by: Songjun Wu <songjun.wu@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* gpio: Add driver for TI PCF8575 I2C GPIO expanderVignesh R2016-08-081-0/+71
| | | | | | | | | | | | | | | | | | TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a 16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. The I/Os should be high before being used as inputs. Read the device documentation for more details[1]. This driver is based on pcf857x driver available in Linux v4.7 kernel. It supports basic reading and writing of gpio pins. [1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* dt-bindings: add Tegra186 BPMP I2C bindingStephen Warren2016-08-041-0/+42
| | | | | | | | | | | | In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW devices, such as the I2C controller for the power management I2C bus. Software running on other CPUs must perform IPC to the BPMP in order to execute transactions on that I2C bus. This binding describes an I2C bus that is accessed in such a fashion. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dt-bindings: allow child nodes inside the Tegra BPMPStephen Warren2016-08-041-0/+23
| | | | | | | | | | The BPMP implements some services which must be represented by separate nodes. For example, it can provide access to certain I2C controllers, and the I2C bindings represent each I2C controller as a device tree node. Update the binding to describe how the BPMP supports this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: add BPMP DT bindingsStephen Warren2016-08-041-0/+81
| | | | | | | | | | | The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. These bindings dictate how to represent the BPMP in device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: adapt to latest HSP DT bindingStephen Warren2016-08-041-0/+52
| | | | | | | | | | The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* serial_sh: Add standrad SCI (w/o FIFO) supportYoshinori Sato2016-07-091-1/+1
| | | | | | | Add support for standard type SCI (without FIFO) port. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit (git 2.34.1) at 2024-10-02 12:35:57 +0000