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cpu
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Author
Age
Files
Lines
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Blackfin: unify cpu and boot modes
Mike Frysinger
2008-03-30
71
-8702
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+2142
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85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Kumar Gala
2008-03-26
2
-0
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+15
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85xx: Update multicore boot mechanism to ePAPR v0.81 spec
Kumar Gala
2008-03-26
4
-64
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+115
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85xx: Fix merge duplication
Kumar Gala
2008-03-26
1
-49
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+0
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85xx: Speed up get_ddr_freq() and get_bus_freq()
James Yang
2008-03-26
1
-16
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+5
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85xx: Show DDR memory data rate in addition to the memory clock frequency.
James Yang
2008-03-26
1
-3
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+6
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85xx: get_tbclk() speed up and rounding fix
James Yang
2008-03-26
1
-5
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+3
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Update SVR numbers to expand support
Andy Fleming
2008-03-26
2
-38
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+49
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85xx: Added support for multicore boot mechanism
Kumar Gala
2008-03-26
1
-0
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+49
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85xx: Added support for multicore boot mechanism
Kumar Gala
2008-03-26
6
-0
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+405
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85xx: Add the concept of CFG_CCSRBAR_PHYS
Kumar Gala
2008-03-26
1
-3
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+3
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Merge branch 'new-image' of git://www.denx.de/git/u-boot-testing
Bartlomiej Sieka
2008-03-26
2
-2
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+2
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Merge branch 'master' of git://www.denx.de/git/u-boot into new-image
Marian Balakowicz
2008-03-12
5
-17
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+44
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Merge branch 'master' of git://www.denx.de/git/u-boot into new-image
Marian Balakowicz
2008-02-29
10
-86
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+72
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[new uImage] Pull in libfdt if CONFIG_FIT is enabled
Marian Balakowicz
2008-02-21
3
-3
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+3
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mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups
Anton Vorontsov
2008-03-25
1
-0
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+8
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83xx: serdes setup routines
Anton Vorontsov
2008-03-25
2
-0
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+146
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83xx: split COBJS onto separate lines
Anton Vorontsov
2008-03-25
4
-11
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+12
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mpc8323erdb: Improve the system performance
Michael Barkowski
2008-03-25
1
-0
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+6
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Coding Style cleanyp; update CHANGELOG
Wolfgang Denk
2008-03-26
1
-2
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+0
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Merge branch 'master' of git://www.denx.de/git/u-boot-mips
Wolfgang Denk
2008-03-26
3
-106
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+186
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[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Shinya Kuribayashi
2008-03-25
1
-5
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+9
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[MIPS] Fix dcache_status()
Shinya Kuribayashi
2008-03-25
1
-3
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+7
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[MIPS] Introduce _machine_restart
Shinya Kuribayashi
2008-03-25
1
-7
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+6
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[MIPS] Cleanup CP0 Status initialization
Shinya Kuribayashi
2008-03-25
1
-9
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+25
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[MIPS] Initialize CP0 Cause before setting up CP0 Status register
Shinya Kuribayashi
2008-03-25
1
-3
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+3
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[MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()
Shinya Kuribayashi
2008-03-25
1
-8
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+0
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[MIPS] Implement flush_cache()
Shinya Kuribayashi
2008-03-25
1
-0
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+22
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[MIPS] Fix I-/D-cache initialization loops
Shinya Kuribayashi
2008-03-25
1
-39
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+76
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[MIPS] Replace memory clearance code with f_fill64
Shinya Kuribayashi
2008-03-25
1
-15
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+28
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[MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros
Shinya Kuribayashi
2008-03-25
1
-18
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+7
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[MIPS] Request for the 'mips_cache_lock()' removal
Shinya Kuribayashi
2008-03-25
2
-0
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+4
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MPC5200: support setup without FEC
André Schwarz
2008-03-25
1
-0
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+4
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8xx: Update OF support on 8xx
Bryan O'Donoghue
2008-03-25
4
-12
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+72
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LWMON5: POST RTC fix
Yuri Tikhonov
2008-03-20
1
-1
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+3
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ppc4xx: Add Canyonlands NAND booting support
Stefan Roese
2008-03-15
1
-1
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+7
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ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)
Stefan Roese
2008-03-15
5
-7
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+178
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ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)
Stefan Roese
2008-03-15
5
-93
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+553
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ppc4xx: interrupt.c reworked
Stefan Roese
2008-03-15
1
-448
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+141
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ppc4xx: program_tlb now uses 64bit physical addess
Stefan Roese
2008-03-15
1
-13
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+14
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ppc4xx: miiphy.c reworked
Stefan Roese
2008-03-15
1
-116
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+80
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PPC4xx (Sequoia): Fix Ethernet "remote fault" problems
Mike Nuss
2008-03-04
1
-3
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+2
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ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
Stefan Roese
2008-03-02
1
-2
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+3
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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Wolfgang Denk
2008-03-02
2
-6
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+14
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85xx: Don't icbi when unlocking the cache
Kumar Gala
2008-02-27
1
-5
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+2
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Fix source for ECM error IVPR
Andy Fleming
2008-02-27
1
-1
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+1
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Invalidate INIT_RAM TLB mappings
Andy Fleming
2008-02-27
1
-0
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+11
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MPC5121e ADS PCI support take 3
John Rigby
2008-03-02
1
-5
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+16
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ppc4xx: Fix problem in 4xx_enet.c driver
Anatolij Gustschin
2008-03-02
1
-1
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+9
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Coding style cleanup. Prepare v1.3.2-rc2 release candidate
v1.3.2-rc2
Wolfgang Denk
2008-02-24
1
-8
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+10
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