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* configs: Resync with savedefconfigTom Rini2020-10-091-1/+1
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_MMC_ENV_DEV et al to KconfigTom Rini2020-08-081-0/+1
| | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_PART Note that with this conversion we now have consistent behavior with respect to ensuring that we have always selected the correct MMC device and hardware partition. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_ENV_OVERWRITE to KconfigAdam Ford2020-07-281-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2020-07-281-1/+1
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* imx8m: Refactor the OPTEE memory removalPeng Fan2020-07-141-1/+0
| | | | | | | | | | | | | | | Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Tested-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* configs: Resync with savedefconfigTom Rini2020-07-061-1/+1
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2020-06-231-1/+1
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* imx: imx8mp_evk: fix boot issuePeng Fan2020-06-081-1/+2
| | | | | | | | | | | The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue. Reported-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx8mp_evk: Select the watchdog driverFabio Estevam2020-06-081-1/+0
| | | | | | | | | | Currently watchdog driver is not selected, which causes system to reboot after staying 60s in the U-Boot prompt. Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be properly serviced. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* ARM: imx8m: Fix reset in SPL on NXP iMX8MP EVKMarek Vasut2020-05-011-0/+4
| | | | | | | | | | | | | | | | | | | Board files should not re-implement do_reset() to work around this function not being defined in for specific configurations. Rather, the fix is to compile in drivers which implement this properly. This patch enables sysreset and watchdog drivers in SPL and ties them together to implement the same as the do_reset() hack in the board file, except correctly in the DM/DT framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Flavio Suligoi <f.suligoi@asem.it> Cc: Harald Seiler <hws@denx.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx8: Run SPL with caches enabledFabio Estevam2020-05-011-2/+0
| | | | | | | | | | | | It is safe to run SPL with caches enabled on i.MX8, so remove such restriction. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oliver Graute <oliver.graute@kococonnector.com> Acked-by: Anatolij Gustschin <agust@denx.de> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* configs: Resync with savedefconfigTom Rini2020-04-281-2/+2
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2020-01-221-5/+5
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* imx: add i.MX8MP EVK boardPeng Fan2020-01-081-0/+84
Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
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