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* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+1
| | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* x86: Add chromebook_coralSimon Glass2019-12-155-0/+88
| | | | | | | | | Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: rk3399: Migrate to use common board fileKever Yang2019-07-291-5/+0
| | | | | | | Use common board file for board_init() and board_late_init(), for Rockchip SoCs have very similar process. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: Move veyron_init() back to veyron.cKever Yang2019-07-291-0/+63
| | | | | | | The veyron_init() should go to its board file veyron.c, and the board_early_init_f() could be the right place. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: move board_early_init_f() back to veyronKever Yang2019-07-291-0/+20
| | | | | | | The board_early_init_f() is only used by veyron board now, move it into the board file veyron.c Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3399: move chromebook bob specific flow to its board fileKever Yang2019-07-291-0/+21
| | | | | | | Add a board_early_init_f() in board_init_f() and move the board specific init code into its own board file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* x86: samus: Add a target to boot through TPLSimon Glass2019-05-083-2/+27
| | | | | | | | | Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: Add MAINTAINER entry for chromebook_speedyPhilipp Tomsich2019-02-011-0/+7
| | | | | | | | | | | This adds a MAINTAINER entry for chromebook_speedy. Without this, we get the following warnings from the maintainers check: WARNING: no status info for 'chromebook_minnie' WARNING: no maintainers for 'chromebook_minnie' Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: Add support for chromebook_bobSimon Glass2019-02-014-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: add support for veyron-speedy (ASUS Chromebook C201)Marty E. Plummer2019-02-011-0/+16
| | | | | | | | | | | This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0710-25/+10
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: kconfig: Remove meaningless 'select n'Ulf Magnusson2018-01-301-1/+0
| | | | | | | | | | | | | | 'select n' selects a constant symbol, which is meaningless and has no effect. Maybe this was meant to be a 'default n', though bool and tristate symbols already implicitly default to n. Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib), which does more strict checking here: kconfiglib.KconfigSyntaxError: board/google/Kconfig:34: Couldn't parse ' select n': expected nonconstant symbol Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: kconfig: Let board select SPI flashBin Meng2017-08-013-0/+3
| | | | | | | | | | Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Select ARCH_EARLY_INIT_R in the platform KconfigBin Meng2017-08-013-23/+0
| | | | | | | | | This is architecture-dependent early initialization hence should be put in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Let board select BOARD_EARLY_INIT_FBin Meng2017-08-013-15/+0
| | | | | | | | | CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: Correct MAINTAINER entry for chromebook_minnieSimon Glass2017-02-091-2/+2
| | | | | | | | | | | This is wrong at present, so genboardscfg.py gives the following warnings: WARNING: no status info for 'chromebook_minnie' WARNING: no maintainers for 'chromebook_minnie' Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: link: Add a config for 64-bit U-BootSimon Glass2017-02-073-1/+15
| | | | | | | | | | | | | | Add a new board config which uses 64-bit U-Boot. This is not fully functional but is it a start. Missing features: - SDRAM sizing - Booting linux - EFI support - SCSI device init (and others) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: link: Add a text base for 64-bit U-BootSimon Glass2017-02-071-1/+2
| | | | | | | Set up the 64-bit U-Boot text base if building for that target. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: Add support for veyron-minnie (ASUS Chromebook Flip)Simon Glass2016-11-252-0/+23
| | | | | | | | This adds support for the Asus Chromebook Flip, an RK3288-based clamshell device which can flip into 'tablet' mode. The device tree file comes from Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add support for veyron-mickey (Chromebit)Simon Glass2016-11-252-0/+23
| | | | | | | | This adds support for the Asus Chromebit, and RK3288-based device designed to plug directly into an HDMI monitor. The device tree file comes from Linux v4.8. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: veyron: Add a note about the SDRAM voltageSimon Glass2016-11-251-0/+6
| | | | | | | Add a comment to indicate that we are not supporting the PWM regulator yet. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename jerry files to veyronSimon Glass2016-11-254-5/+5
| | | | | | | | | | | At present we have a single rk3288-based Chromebook: chromebook_jerry. But all such Chromebooks can use the same binary with only device-tree differences. The family name is 'veyron', so rename the files accordingly. Also update the device-tree filename since this currently differs from Linux. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for the samus chromebookSimon Glass2016-03-175-0/+84
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop all the old pin configuration codeSimon Glass2016-03-172-142/+0
| | | | | | | | We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-241-8/+0
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Do not require HAVE_INTEL_MEBin Meng2016-01-132-0/+2
| | | | | | | | | Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-092-2/+0
| | | | | | | | | These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng2015-12-092-2/+0
| | | | | | | | | | This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Clean up ivybridge/chrome Kconfig optionsBin Meng2015-12-092-2/+0
| | | | | | | | | | There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for jerrySimon Glass2015-09-025-1/+36
| | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove MARK_GRAPHICS_MEM_WRCOMBBin Meng2015-07-142-2/+0
| | | | | | | | MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* arch: Make board selection choices optionalJoe Hershberger2015-05-121-0/+1
| | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONSBin Meng2015-04-292-0/+6
| | | | | | | | | Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-291-0/+43
| | | | | | | | | | Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: cros_ec: Drop unnecessary initSimon Glass2015-04-181-3/+0
| | | | | | | Since driver model will probe the EC when it is first used, we do not need to init it explicitly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass2015-04-181-0/+9
| | | | | | Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for panther (Asus Chromebox)Simon Glass2015-04-164-0/+69
| | | | | | | | | | | | | | | | | | | | Support running U-Boot as a coreboot payload. Tested peripherals include: - Video (HDMI and DisplayPort) - SATA disk - Gigabit Ethernet - SPI flash USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work. For video, coreboot will need to run the OPROM to set this up. With this board, bare support (running without coreboot) is not available as yet. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-051-2/+1
| | | | | | | | | This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move CONFIG_SYS_CAR_xxx to KconfigBin Meng2015-01-131-0/+8
| | | | | | | | | | Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng2015-01-131-0/+1
| | | | | | | | Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-181-1/+1
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-131-0/+40
| | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Make ROM_SIZE configurable in KconfigBin Meng2014-12-131-0/+1
| | | | | | | | | | Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_link: Enable the Chrome OS ECSimon Glass2014-11-251-0/+4
| | | | | | Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove board_early_init_r()Simon Glass2014-11-251-5/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-211-0/+107
| | | | | | | Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-211-0/+12
| | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-212-1/+24
| | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add chromebook_link boardSimon Glass2014-11-216-0/+70
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-07-05 15:35:28 +0000