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* Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.stroese2003-04-041-1/+7
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* Make compile clean, fix the usual small problems.LABEL_2003_03_26_1300wdenk2003-03-261-1/+0
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* esd PCI405 updated.stroese2003-03-261-0/+32
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* esd PCI405 updated.stroese2003-03-254-782/+1015
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* CPCI4052 update (support for revision 3).stroese2003-03-203-816/+888
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* Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).stroese2003-02-141-1/+1
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* Initial revisionwdenk2002-11-032-0/+953
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* Initial revisionwdenk2002-11-034-0/+475
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* Initial revisionwdenk2002-11-036-0/+1405
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* Initial revisionwdenk2002-09-201-0/+738
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* Initial revisionwdenk2002-09-188-0/+774
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* Initial revisionwdenk2002-08-303-0/+586
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* Initial revisionwdenk2002-08-263-0/+448
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* Initial revisionwdenk2002-08-178-0/+1612
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* Initial revisionwdenk2002-08-141-0/+156
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* Initial revisionwdenk2002-08-063-0/+240
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* Initial revisionwdenk2002-07-203-0/+426
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* Initial revisionwdenk2002-07-181-0/+32
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* Initial revisionwdenk2002-07-073-0/+138
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* Initial revisionwdenk2002-06-072-0/+772
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* Initial revisionwdenk2002-05-151-0/+342
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* Initial revisionwdenk2002-04-012-0/+92
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* Initial revisionwdenk2002-03-021-0/+703
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* Initial revisionwdenk2001-12-283-0/+478
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* Initial revisionwdenk2001-11-262-0/+4818
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* Initial revisionwdenk2001-10-151-0/+29
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* Initial revisionwdenk2001-10-073-0/+103
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* Initial revisionwdenk2001-08-055-0/+2192
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* Initial revisionwdenk2001-07-195-0/+205