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* Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.stroese2003-04-041-1/+7
* Make compile clean, fix the usual small problems.LABEL_2003_03_26_1300wdenk2003-03-261-1/+0
* esd PCI405 updated.stroese2003-03-261-0/+32
* esd PCI405 updated.stroese2003-03-254-782/+1015
* CPCI4052 update (support for revision 3).stroese2003-03-203-816/+888
* Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).stroese2003-02-141-1/+1
* Initial revisionwdenk2002-11-032-0/+953
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