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| * | arm: stm32mp: bsec: migrate trace to log macroPatrick Delaunay2021-01-131-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | Define LOG_CATEGORY, change pr_debug to dev_dbg and remove "bsec:" header as it is managed by log macro (dev->name is displayed) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | arm: stm32mp: migrate cmd_stm32prog to log macroPatrick Delaunay2021-01-135-78/+78
| | | | | | | | | | | | | | | | | | | | | Change debug and pr_ macro to log macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | arm: stm32mp: migrate trace to log macroPatrick Delaunay2021-01-137-29/+43
| |/ | | | | | | | | | | | | Change debug and pr_ macro to log macro and define LOG_CATEGORY. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini2021-01-1326-905/+2391
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
| * ARM: dts: import Beelink GT-King/Pro DTs from Linux 5.10Christian Hewitt2021-01-114-0/+697
| | | | | | | | | | | | | | | | Import the Beelink GT-King/Pro and supporting meson-g12b-w400.dtsi file from Linux 5.10. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: import WeTek Core2 DTs from Linux 5.10Christian Hewitt2021-01-114-0/+419
| | | | | | | | | | | | | | | | Import the WeTek Core2 and supporting meson-gx-p23x-q20x.dtsi files from Linux 5.10. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * meson: Add soc_rev to environmentPascal Vizeli2021-01-112-0/+16
| | | | | | | | | | | | | | | | | | | | Add SoC revision to environment. This can be useful to select the correct device tree at runtime (N2/N2+). Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: meson: isolate loading of socinfoStefan Agner2021-01-111-1/+13
| | | | | | | | | | | | | | | | | | Move loading of socinfo into a separate function so the value can be reused later. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * arm64: meson: add support for libretech-cc v2Jerome Brunet2021-01-111-0/+7
| | | | | | | | | | | | | | | | | | Add support for the Amlogic based libretech cc version 2. As version 1, it is based on the s905x SoC. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: Fixed libretech-cc.rst bullet points] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * arm64: dts: import libretech-cc-v2 from linux v5.10-rc1Jerome Brunet2021-01-112-0/+319
| | | | | | | | | | | | | | | | Sync the libretech cc v2 device tree from Linux v5.10-rc1 commit 3650b228f83a ("Linux 5.10-rc1") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: sync Amlogic GX & AXG from Linux 5.10-rc1Neil Armstrong2021-01-1116-904/+920
| | | | | | | | | | | | Synced from Linux commit 3650b228f83a ("Linux 5.10-rc1") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge tag 'ti-v2021.04-rc1' of ↵Tom Rini2021-01-1238-811/+2767
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - DM support for OMAP PWM backlight - USB host mode support for AM654 - Minor SPI fixes - Add support k2g ice board with 1GHz silicon - Fix GTC programming for K3 devices
| * | arm: dts: k3-*-r5-*-board: Add GTC clockNishanth Menon2021-01-123-0/+3
| | | | | | | | | | | | | | | | | | | | | Add GTC Clock definition as index 0 clock so that we can use the clock node in the driver later on. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | video: omap: drop domain clock enabling by SOC apiDario Binacchi2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | Enabling the domain clock is performed by the sysc interconnect target module driver during the video device probing. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | video: omap: add panel driverDario Binacchi2021-01-1211-44/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous version of am335x-fb.c contained the functionalities of two drivers that this patch has split. It was a video type driver that used the same registration compatible string that now registers a panel type driver. The proof of this is that two compatible strings were referred to within the same driver. There are now two drivers, each with its own compatible string, functions and API. Furthermore, the panel driver, in addition to decoding the display timings, is now also able to manage the backlight. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: core: add a function to decode display timingsDario Binacchi2021-01-121-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds a function to get display timings from the device tree node attached to the device. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: dts: am335x: enable scm_clocks auto bindingDario Binacchi2021-01-122-0/+16
| | | | | | | | | | | | | | | | | | | | | Adding the 'simple-bus' compatible string to the scm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | fdt: translate address if #size-cells = <0>Dario Binacchi2021-01-121-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __of_translate_address routine translates an address from the device tree into a CPU physical address. A note in the description of the routine explains that the crossing of any level with since inherited from IBM. This does not happen for Texas Instruments, or at least for the beaglebone device tree. Without this patch, in fact, the translation into physical addresses of the registers contained in the am33xx-clocks.dtsi nodes would not be possible. They all have a parent with #size-cells = <0>. The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation possible even in the case of crossing levels with #size-cells = <0>. The patch acts conservatively on address translation, except for removing a check within the of_translate_one function in the drivers/core/of_addr.c file: + ranges = of_get_property(parent, rprop, &rlen); - if (ranges == NULL && !of_empty_ranges_quirk(parent)) { - debug("no ranges; cannot translate\n"); - return 1; - } if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); debug("empty ranges; 1:1 translation\n"); There are two reasons: 1 The function of_empty_ranges_quirk always returns false, invalidating the following if statement in case of null ranges. Therefore one of the two checks is useless. 2 The implementation of the of_translate_one function found in the common/fdt_support.c file has removed this check while keeping the one about the 1:1 translation. The patch adds a test and modifies a check for the correctness of an address in the case of enabling translation also for zero size cells. The added test checks translations of addresses generated by nodes of a device tree similar to those you can find in the files am33xx.dtsi and am33xx-clocks.dtsi for which the patch was created. The patch was also tested on a beaglebone black board. The addresses generated for the registers of the loaded drivers are those specified by the AM335x reference manual. Signed-off-by: Dario Binacchi <dariobin@libero.it> Tested-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: dts: am335x: enable prcm_clocks auto bindingDario Binacchi2021-01-121-0/+4
| | | | | | | | | | | | | | | | | | | | | Adding the 'simple-bus' compatible string to the prcm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | ti: am33xx: fix do_enable_clocks() to accept NULL parametersDario Binacchi2021-01-121-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Up till this commit passing NULL as input parameter was allowed, but not handled properly. When a NULL parameter was passed to the function a data abort was raised. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: dts: am335x: include am33xx-u-boot.dtsiDario Binacchi2021-01-1211-0/+23
| | | | | | | | | | | | | | | | | | Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macroDario Binacchi2021-01-121-0/+1
| | | | | | | | | | | | | | | | | | | | | Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | clk: add clk_round_rate()Dario Binacchi2021-01-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * | arm: dts: sync am33xx with Linux 5.9-rc7Dario Binacchi2021-01-1210-542/+2273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been several changes to the am33xx.dtsi, so this patch re-syncs it with Linux. Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel. With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. The am33xx-clock.dtsi file is the same as that of the Linux kernel, except for the reg property of the node l4-wkup-clkctrl@0. As for the am33xx.dtsi file, all the devices with drivers not yet implemented and those I was able to test with this patch have been moved to am33xx-l4.dtsi. In case of any regressions, problem devices can be reverted by moving them back and removing the related interconnect target module node. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | bus: ti: add minimal sysc interconnect target driverDario Binacchi2021-01-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * | arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config toolPraneeth Bajjuri2021-01-122-219/+219
| | | | | | | | | | | | | | | | | | | | | | | | Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
| * | arm: dts: am654-base-board-uboot: Add aliases for USB subsystemsAswath Govindraju2021-01-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: am654-base-board-uboot: Set USB0 dr_mode to hostAswath Govindraju2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | USB3SS0 controller is to be used as a host in U-boot. Fix it by changing the dr_mode to host. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
* | | Merge tag 'u-boot-atmel-2021.04-a' of ↵Tom Rini2021-01-125-0/+448
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2021.04 cycle This feature set includes the new board SAMA7G5 EK, the new evaluation kit for Microchip AT91 SAMA7G5 SoC . The current board support includes two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and support for two Ethernet interfaces.
| * | | ARM: dts: sama7g5ek: fix TXC pin configurationNicolas Ferre2021-01-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TXC line is directly connected from the SoC to the KSZ9131 PHY. There is a transient state on this signal, before configuring it to RGMII, which leads to packet transmit being blocked. Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
| * | | ARM: dts: sama7g5ek: add i2c1 bus and eepromsEugen Hristev2021-01-071-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add node for flx1 i2c1 subnode (and alias to bus 0) This bus has two eeprom devices connected. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add flexcom1 and i2c subnodeEugen Hristev2021-01-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Add flexcom1 and i2c subnode. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5ek: enable sdmmc0 with pinctrlEugen Hristev2021-01-071-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable sdmmc0 on this board. A non-removable eMMC is connected on this block. Configure pincontrol accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add node for sdmmc0Eugen Hristev2021-01-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add node for sdmmc0 block. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add assigned clocks for sdmmc1Eugen Hristev2021-01-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SDMMC1 requires clock specification with assigned-clocks, such that the PMC will know which parent to assign and the initial start-up frequency. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add GMAC1Claudiu Beznea2021-01-072-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Add GMAC1. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add GMAC0Claudiu Beznea2021-01-072-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Add GMAC0. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3Eugen Hristev2021-01-072-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl for sdmmc1 and flx3. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add pinctrl nodeEugen Hristev2021-01-072-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add pioA pinctrl node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add pit64b supportClaudiu Beznea2021-01-072-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PIT64B driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add CPU bindingsClaudiu Beznea2021-01-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add CPU DT bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: switch to PMC bindingsClaudiu Beznea2021-01-072-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of software defined MCK and switch to PMC bindings for IPs currently present in device tree. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add PMC bindingsClaudiu Beznea2021-01-072-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow clock bindingsClaudiu Beznea2021-01-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for slow clock driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtalsClaudiu Beznea2021-01-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add dm-pre-reloc DT binding property for cristals. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow rc and main rc oscillatorsClaudiu Beznea2021-01-072-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add slow rc and main rc oscillators to dtsi. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: move clock frequencies for xtals in board fileClaudiu Beznea2021-01-072-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Move clock frequencies for crystals on board specific files. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: add initial support for sama7g5ekEugen Hristev2021-01-074-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | Add initial support for sama7g5 evaluation kit board. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add initial DT for sama7g5 SoCEugen Hristev2021-01-071-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* | | | sunxi: board: add a config option to fixup a Bluetooth addressAndre Heider2021-01-111-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, ship with the controller default address. Add a config option to fix it up so it can function properly. Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <mripard@kernel.org> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit (git 2.34.1) at 2025-10-01 14:50:44 +0000