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* | | Merge tag 'u-boot-atmel-2021.04-b' of ↵Tom Rini2021-01-256-5/+142
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.04 cycle This feature set includes macb updates for all interfaces and new sama7g5 variant support; micrel ksz9031 DLL support; a new board from Giant based on Adafruit feather form factor which contains a SAMA5D27 SoC; several fixes regarding the NAND flash PMECC block; and pincontrol drive strength support for pio4 controller.
| * | ARM: at91: spl: add spl_early_init for sama5d2 platformsGreg Gallagher2021-01-221-0/+7
| | | | | | | | | | | | | | | | | | | | | The dm root node is needed early in the spl to allow the timer to be used. This change calls spl_early_init to initialize the dm root node. Signed-off-by: Greg Gallagher <greg@embeddedgreg.com>
| * | board: atmel: Add SAMA5D27 giant boardGreg Gallagher2021-01-222-1/+130
| | | | | | | | | | | | | | | | | | | | | | | | Giant board is a tiny SBC based on the Adafruit Feather form factor, created by groboards it contains a SAMA5D2 processor (SAMA5D27), 128 MB of RAM and a microSD card for storage. Signed-off-by: Greg Gallagher <greg@embeddedgreg.com>
| * | sam9x60.h: Fix Galois Field Table offsetsKai Stuhlemmer (ebee Engineering)2021-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because ATMEL_BASE_ROM is defined to 0x100000, it already points to the begin of the index table for 512 byte sectors correction. Thus its offset must be zero and the index of the table for 1024 byte sectors must start at offset 0x8000. Signed-off-by: Kai Stuhlemmer (ebee Engineering) <kai.stuhlemmer@ebee.de> [ta: update commit message] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | sama5d3: Fix Galois Field Table offsetsTudor Ambarus2021-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Offsets are described in the datasheet at section: "11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction". For testing I "injected" bit flips into u-boot NAND memory area, and then read back. PMECC could not correct the errors. With the offsets updated everything is fine. Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | pinctrl: at91-pio4: implement drive strength supportEugen Hristev2021-01-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.gitTom Rini2021-01-221-2/+0
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| * | samsung: arndale: remove board_mmc_init functionJaehoon Chung2021-01-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove board_mmc_init function. It will be probed with driver-model. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | rockchip: rk3328: Add support for FriendlyARM NanoPi R2SDavid Bauer2021-01-213-0/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the NanoPi R2S from FriendlyArm. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer <mail@david-bauer.net> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | arm: dts: rockchip: rk3399: enable rng at the SoC levelPeter Robinson2021-01-214-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rng is embedded in the SoC so enable it in the device tree universally, the use of it can be controlled by enabling/disabling at the device config level. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | rockchip: leez-rk3399: Provide init voltageKever Yang2021-01-211-0/+4
| | | | | | | | | | | | | | | | | | Add missing regulator-init-microvolt property to vdd_log regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | rockchip: firefly-rk3399: Provide init voltageKever Yang2021-01-211-0/+4
| | | | | | | | | | | | | | | | | | Add missing regulator-init-microvolt property to vdd_log regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | rockchip: evb-rk3399: Provide init voltageKever Yang2021-01-211-0/+4
| | | | | | | | | | | | | | | | | | Add missing regulator-init-microvolt property to vdd_center regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | rockchip: puma-haikou: default to SPI bus 1 for SPI-flashHugh Cole-Baker2021-01-211-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI flash on this machine is located on bus 1, default to using bus 1 for SPI flash and stop aliasing it to bus 0. Formerly the alias spi1 pointed to &spi5, use an alias spi5 for this instead. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | rockchip: rk3399-roc-pc: default to SPI bus 1 for SPI-flashHugh Cole-Baker2021-01-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI flash on this board is located on bus 1, default to using bus 1 for SPI flash on both rk3399-roc-pc and -mezzanine, and stop aliasing it to bus 0. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | dts: mt7622: use accurate clock source fot mtk_timerWeijie Gao2021-01-181-7/+1
| | | | | | | | | | | | | | | | | | | | | The input system clock for mt7622 timer is 10MHz and can be retrieved through the clk driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | | aspeed: Add AST2600 platform supportChia-Wei, Wang2021-01-189-0/+461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | ARM: dts: aspeed: Add AST2600 SoC supportChia-Wei, Wang2021-01-184-0/+2170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | wdt: aspeed: Add AST2600 watchdog supportChia-Wei, Wang2021-01-181-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | ram: aspeed: Add AST2600 DRAM control supportDylan Hung2021-01-181-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | clk: aspeed: Add AST2600 clock supportRyan Chen2021-01-181-0/+338
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
* | | board: presidio: Add Parallel NAND supportKate Liu2021-01-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set environment for Nand flash (U-boot 2020.04): - add nand flash in the device tree - add new default configuration file for G3 using parallel Nand - set nand parameters in presidio_asic.h Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | acpi: Add missing ARM acpi_table headerHarm Berntsen2021-01-181-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h by proxy. This file does not exist for the ARM architecture and thus code compilation failed when using this driver on ARM. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | gpio: do not include <asm/arch/gpio.h> on ARCH_QEMUHarm Berntsen2021-01-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for QEMU. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
* | | arm: dts: mt8516-pumpkin: enable usb portFabien Parent2021-01-181-0/+10
| | | | | | | | | | | | | | | | | | Enable the USB port for MT8516 Pumpkin Board. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* | | arm: dts: mt8516: add support for USBFabien Parent2021-01-181-0/+14
| |/ |/| | | | | | | | | Add support for USB on mt8516 based SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2021-01-188-8/+8
|\ \ | | | | | | | | | - R-Car pinctrl updates
| * | ARM: dts: renesas: Remove leading 0x from rpc nodeLad Prabhakar2021-01-188-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the leading "0x" from rpc node to fix the below dtc warning: Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit address format error, expected "ee200000" Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-01-185-0/+444
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - Select TIMER_EARLY to avoid infinite recursion for Trace.
| * | | riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari2021-01-183-0/+436
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * | | riscv: Add DMA 64-bit address supportPadmarao Begari2021-01-182-0/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
* / / armv8: Makefile: build cache files when neededPeng Fan2021-01-161-1/+3
|/ / | | | | | | | | | | If no need cache support, not build the cache files, such as in SPL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | common: board_r: Drop arch-specific ifdefs around initr_trapOvidiu Panait2021-01-154-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | In order to remove the arch-specific ifdefs around initr_trap, introduce arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have been moved to arch/<arch>/lib/traps.c Default implementation is a nop stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | common: board_r: Drop initr_noncached wrapperOvidiu Panait2021-01-152-2/+15
| | | | | | | | | | | | | | | | Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | common: board_r: Drop initr_secondary_cpu wrapperOvidiu Panait2021-01-151-1/+3
| | | | | | | | | | | | | | | | Add a return value to cpu_secondary_init_r and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | test: add test for dropped trace before log_initPatrick Delaunay2021-01-151-0/+5
| | | | | | | | | | | | | | Add test for dropped trace before log_init, displayed by debug uart. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: socfpga: soc64: Enable FIT image generation using binmanSiew Chin Lim2021-01-151-0/+2
| | | | | | | | | | | | | | Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: dts: soc64: Add binman node of FIT image with ATF supportSiew Chin Lim2021-01-154-2/+134
| | | | | | | | | | | | | | | | | | | | | | | | Add binman node to device tree to generate the FIT image for u-boot (u-boot.itb) and OS kernel (kernel.itb). u-boot.itb contains arm trusted firmware (ATF), u-boot proper and u-boot device tree for ATF u-boot flow. kernel.itb contains Linux Image and Linux device tree. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: soc64: Skip handoff data access in SSBLChee Hong Ang2021-01-151-1/+2
| | | | | | | | | | | | | | | | SPL already setup the Clock Manager with the handoff data from OCRAM. When the Clock Manager's driver get probed again in SSBL, it shall skip the handoff data access in OCRAM. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()Chee Hong Ang2021-01-151-0/+5
| | | | | | | | | | | | | | mbox_reset_cold() will invoke ATF's PSCI service when running in non-secure mode (EL2). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | arm: socfpga: soc64: Add ATF support for Reset Manager driverChee Hong Ang2021-01-151-0/+13
| | | | | | | | | | | | | | | | | | In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service provided by ATF to enable/disable the SOCFPGA bridges. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Add secure register access helper functions for SoC 64bitsSiew Chin Lim2021-01-153-0/+109
| | | | | | | | | | | | | | | | | | These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)Chee Hong Ang2021-01-153-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | invoke_smc() allow U-Boot proper running in non-secure mode (EL2) to invoke SMC call to ATF's PSCI runtime services such as System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. smc_send_mailbox() is a send mailbox command helper function which invokes the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD) to send mailbox messages to Secure Device Manager (SDM). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | arm: socfpga: Disable "spin-table" method for booting LinuxChee Hong Ang2021-01-151-2/+0
| | | | | | | | | | | | | | | | Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | arm: socfpga: soc64: Override 'lowlevel_init' to support ATFChee Hong Ang2021-01-152-0/+78
| | | | | | | | | | | | | | | | | | Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | arm: socfpga: Add function for checking description from FIT imageChee Hong Ang2021-01-151-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add board_fit_config_name_match() for matching board name with device tree files in FIT image. This will ensure correct DTB file is loaded for different board type. Currently, we are not supporting multiple device tree files in FIT image therefore this function basically do nothing for now. Users are allowed to override this 'weak' function in their specific board implementation. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* | Merge tag 'u-boot-stm32-20210113' of ↵Tom Rini2021-01-1321-144/+175
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Enable logging features for stm32mp15 boards - Update MAINTAINERS emails for STI and STM32 - Activate OF_LIVE for ST stm32mp15 boards - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards - Correction in stm32prog command on uart: always flush DFU on start command - Update USB-C power detection algorithm on DK boards
| * | MAINTAINERS: Update STi and STM32 maintainers emails in remaining filesPatrice Chotard2021-01-136-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A previous series already update STMicroelectronics emails maintainers but some files have been omitted (Makefile, .dts, .dtsi and .rst files). Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | arm: stm32mp: stm32prog: always flush DFU on start command for uartPatrick Delaunay2021-01-131-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the test on data->dfu_seq, because dfu_seq=0 not only when the DFU is not started (mask with 0xffff). This flush is mandatory as the final treatment, common with USB, is done in DFU callback. This patch avoids issue if the received length is a multiple of the DFU packet. For example if size of bootfs partition is egual to 0x4000000, data->dfu_seq=0 at the end of the partition, the flush it not requested and the phase is not increased in the callback. U-Boot continue to request the bootfs in the next GetPhase command. Fixes: 468f0508b58b ("stm32mp: stm32prog: add serial link support") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clockMarek Vasut2021-01-132-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P. To permit PLL4P to run at faster frequency, use MCO2 as a divider. The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to 50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback clock are fed back in via pin PA1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
generated by cgit (git 2.34.1) at 2025-10-01 11:19:36 +0000