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| * | arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-BootLokesh Vutla2021-02-046-215/+583
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot. MCU R5F nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid regressions, r5f nodes are kept intact. These will be added in kernel in future. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-BootLokesh Vutla2021-02-048-406/+2347
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot. HBMC nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid any regressions, hbmc nodes are kept intact. These will be added in kernel in future. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-BootLokesh Vutla2021-02-049-376/+1360
| | | | | | | | | | | | | | | | | | Sync all AM65 related v5.11-rc6 Linux kernel dts into U-Boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: dts: k3-am654-base-board: Limit Sd card to High speed modesFaiz Abbas2021-02-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's an issue with the base board in which the power cycle circuit takes way longer to power down than expected by mmc core. code. This prevents the card from enumerating in UHS modes. Disable UHS modes for this board until a new board revision fixes the issue. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-am65-main: Add itapdly and clkbuf-sel valuesFaiz Abbas2021-02-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add the appropriate itapdly and clkbuf-sel values required for some lower speed modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-j7200-common-proc-board: Enable support for UHS modesFaiz Abbas2021-02-043-2/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for UHS modes by adding the regulators to power cycle and voltage switch the card. Also add pinmuxes required for each node Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-j7200-main: Add support for gpio0Faiz Abbas2021-02-041-0/+22
| | | | | | | | | | | | | | | | | | | | | Add support for the main_gpio0 node Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD cardFaiz Abbas2021-02-041-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add support for regulators to power cycle and switch IO voltage to the SD card. This enables support for UHS modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-j721e-main: Update otap-delay valuesFaiz Abbas2021-02-041-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update otap delay values to match with the latest Data Manual[1]. [1] https://www.ti.com/lit/gpn/dra829v Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: k3-am65: Fix mmc nodesFaiz Abbas2021-02-044-60/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of fundamental interface issues in am65x pg1, only the initial sdhci1 node at 25 MHz was added in the u-boot.dtsi from which both the base-board.dts and r5-base-board.dts inherit the node. Move the node out to k3-am65-main.dtsi where it belongs and add the board specific properties in base-board.dts and r5-base-board.dts This ensures dts compatibility with the kernel dts in the base-board.dts and enables the SD card interface at 50 MHz and High Speed mode While we are here, also fix the main_mmc0_pins_default property to be included and inherit from the base-board.dts instead of the u-boot.dtsi Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | remoteproc: k3_r5: Sync to upstreamed kernel DT property namesSuman Anna2021-02-045-42/+42
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the equivalent remoteproc driver in the Linux kernel. Some of the DT properties used in U-Boot got upstreamed using different names in Linux kernel. The modified property names include the R5F cluster mode configuration property "lockstep-mode"; and three different individual R5F core config properties - "atcm-enable", "btcm-enable" and "loczrama". The property names were updated as follows: lockstep-mode => ti,cluster-mode atcm-enable => ti,atcm-enable btcm-enable => ti,btcm-enable loczrama => ti,loczrama Update the K3 R5F remoteproc driver, the corresponding binding, and all the existing usage in AM65x, J721E and J7200 dts files all at once to use the new properties and to not break any bisectability. Signed-off-by: Suman Anna <s-anna@ti.com>
* | Merge tag 'dm-pull-3feb21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2021-02-048-22/+23
|\ \ | | | | | | | | | | | | Support late device removal Allow booting a 32-bit system with a top memory address beyond 4 GiB
| * | bdinfo: Change to use bdinfo_print_num_ll() where the number could be 64-bitBin Meng2021-02-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are some calls to bdinfo_print_num_l() with parameters that could be a 64-bit value on a 32-bit system. Change those calls to use bdinfo_print_num_ll() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | bdinfo: Rename function names to be clearerBin Meng2021-02-033-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we have bdinfo_print_num() to print unsigned long numbers. We also have print_phys_addr() which accept numbers that might be 64-bit on a 32-bit platform. Rename these 2 functions to be clearer: bdinfo_print_num() => bdinfo_print_num_l() print_phys_addr() => bdinfo_print_num_ll() While we are here, make bdinfo_print_num_ll() public so that it can be used outside cmd/bdinfo.c in the future. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * | riscv: Change phys_addr_t and phys_size_t to 64-bitBin Meng2021-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | phys_addr_t and phys_size_t are currently defined as `unsigned long`, but RV32 supports 34-bit physical address, hence both phys_addr_t and phys_size_t should be defined to 64-bit using `unsigned long long`. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * | arm: rockchip: Explicitly cast gd->ram_top in dram_init_banksize()Bin Meng2021-02-031-1/+1
| | | | | | | | | | | | | | | | | | | | | The min() macro used in dram_init_banksize() requires two elements to compare have the same type. Let's explicitly cast gd->ram_top. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * | riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng2021-02-032-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * | arm: Remove vital devices lastSimon Glass2021-02-031-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | Update announce_and_cleanup() to remove all devices, with the vital ones being removed last. This is an extra patch on top of the recent RFC: http://patchwork.ozlabs.org/project/uboot/list/?series=223280 Signed-off-by: Simon Glass <sjg@chromium.org>
* / x86: qemu: Fix broken multi-core bootBin Meng2021-02-031-0/+6
|/ | | | | | | | | | | | | Unfortunately the multi-core boot for QEMU x86 has been broken since commit 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start"). In order to support QEMU x86 multi-core boot, the /cpus node must be bound before any actual fix up in qemu_cpu_fixup(). This adds the uclass_get() call to ensure this, just like what was done before. Fixes: 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Remove #include <version.h> from armv8/fwcall.cPali Rohár2021-02-011-1/+0
| | | | | | | | | No version information is used in armv8/fwcall.c therefore do not include version.h header file. This change prevents recompiling fwcall.o when SOURCE_DATE_EPOCH changes. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tpl: Show next stage being bootedSimon Glass2021-02-011-1/+6
| | | | | | | | Enhance the debugging to show the next stage being booted as well as a dump of the start of the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Clear BSS unconditionallySimon Glass2021-02-011-1/+1
| | | | | | | | This should be done even if not using TPL, since BSS may be in use or boards that only use SPL. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: zimage: Improve command-line debug handlingSimon Glass2021-02-011-3/+7
| | | | | | | | | | At present if the command line is very long it is truncated by the printf() statement, which works within a limited buffer. Use puts() instead. Also show better debugging with the command-line setup fails. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: zimage: Allow dumping the image from outside the moduleSimon Glass2021-02-012-8/+25
| | | | | | | | | | | At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update Chromium OS GNVS namesSimon Glass2021-02-011-6/+28
| | | | | | | | | | | The Global Non-Volatile Storage struct has some fields with particular meanings. Rename these to make things easier to follow. Also add a few more boot flags. GNVS should not be confused with GNVQ (Going Nowhere Very Quickly). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Make moving BSS conditionalSimon Glass2021-02-011-0/+2
| | | | | | | | | At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make sure the SPL image ends on a suitable boundarySimon Glass2021-02-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built with any particular alignment. It ends at the start of the BSS section. The BSS section selects its own alignment, which may larger. This means that there can be a gap of a few bytes between the image ending and BSS starting. Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with perhaps some padding for BSS), the expected result is not obtained. U-Boot uses the end of BSS to find the devicetree, so this means that it cannot be found. Add 32-byte alignment of BSS so that the image size is correct and appending the devicetree will place it at the end of BSS. Example SPL output without this patch: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000142a1 fef40000 fef40000 00001000 2**4 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .u_boot_list 000014a4 fef542a8 fef542a8 000152a8 2**3 CONTENTS, ALLOC, LOAD, RELOC, DATA 2 .rodata 0000599c fef55760 fef55760 00016760 2**5 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA 3 .data 00000970 fef5b100 fef5b100 0001c100 2**5 CONTENTS, ALLOC, LOAD, RELOC, DATA 4 .binman_sym_table 00000020 fef5ba70 fef5ba70 0001ca70 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .bss 00000060 fef5baa0 fef5baa0 00000000 2**5 ALLOC You can see that .bss is aligned to 2**5 (32 bytes). This is because of the mallinfo struct in dlmalloc.c: 17 .bss.current_mallinfo 00000028 00000000 00000000 000004c0 2**5 ALLOC In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up with the _image_binary_end symbol: fef5ba90 g .binman_sym_table 00000000 _image_binary_end But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte alignment. So we must align _image_binary_end to a 32-byte boundary. This forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as expected. Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even though it generates an object file with a member that requests 32-byte alignment. The current_mallinfo struct is 40 bytes in size. Increasing the struct to 68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment to go above 32 bytes. So it seems that 32 bytes is the maximum alignment at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add more details in the commit message to help people understand] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Enhance debugging in the SPL loaderSimon Glass2021-02-011-5/+7
| | | | | | | | Move to log_debug() and make use of the new SPL function to find the text base. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi_gpe: Update driver name to match devicetreeSimon Glass2021-02-011-2/+4
| | | | | | | | Use a driver name in line with the compatible string so that of-platdata can use this driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Add a devicetree node for eMMCSimon Glass2021-02-011-0/+6
| | | | | | | | | Add a node for this so we can indicate that it is does not require any ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2021-01-317-0/+733
|\ | | | | | | - Sync r8a774a1 DT files, tmio sdhi DMA fix
| * arm: dts: rmobile: r8a774a1: Synchronize DTs with Linux 5.10Biju Das2021-01-317-0/+733
| | | | | | | | | | | | | | | | DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and r8a774a1-u-boot.dtsi have been imported from linux 5.10 commit 2c85ebc57b3e1817 ("Linux 5.10"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | Merge tag 'dm-pull-30jan21' of ↵Tom Rini2021-01-319-7/+83
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm tpm fixes for coral binman fixes support for symbols in sub-sections support for additional cros_ec commands various minor fixes / tweaks
| * | sandbox: keep time offset when resettingHeinrich Schuchardt2021-01-301-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UEFI Self Certification Test (SCT) checks the SetTime() service with the following steps: * set date * reset * check date matches To be compliant the sandbox should keep the offset to the host RTC during resets. The implementation uses the environment variable UBOOT_SB_TIME_OFFSET to persist the offset. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Update ofnode_read_fmap_entry() to read hashesSimon Glass2021-01-301-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present this function uses the old format for reading hashes. Add support for the current format. Add a test while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Disable I2C emulators in SPLSimon Glass2021-01-301-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These cannot work with of-platdata since they currently need the devicetree at runtime. Disable the emulators and the sandbox I2C driver that needs them. We can enable these later, if needed for testing. Switch the of_plat_parent test over to use a simple bus instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | x86: coral: Support TPM and RTC in SPLSimon Glass2021-01-302-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | cros_ec: Add support for switchesSimon Glass2021-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 platforms the EC provides a way to read 'switches', which are on/off values determined by the EC. Add a new driver method for this and implement it for LPC. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | cros_ec: Add a function for the hello messageSimon Glass2021-01-301-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is used several times in this file. Put it in a function to avoid code duplication. Also add a test for this function. There are no cros_ec tests at present, so it is time to update the code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: fix sandbox_cmdline_cb_test_fdt()Heinrich Schuchardt2021-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | fmt does not foresee any parameter. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: typo segementHeinrich Schuchardt2021-01-302-2/+2
| | | | | | | | | | | | | | | | | | | | | %s/segement/segment/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: coral: Update an unused pin to reduce powerSimon Glass2021-01-301-0/+1
| |/ | | | | | | | | | | GPIO_25 is not used on coral, so set it up in deep sleep. Signed-off-by: Simon Glass <sjg@chromium.org>
* / efi_loader: add Linux magic to aarch64 crt0Heinrich Schuchardt2021-01-291-1/+2
|/ | | | | | | | Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. Now we can dump the fixed-up device tree with our dtbdump.efi tool. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* arm: dts: enable MTK SPI NOR controller driverSkyLake.Huang2021-01-294-2/+52
| | | | | | | 1. Enable MTK SPI NOR controller driver on mt7622 & mt7629. 2. Enable quad mode for read and single mode for write. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-01-273-11/+27
|\ | | | | | | | | | | | | | | | | | | | | - Espressobin: Disable slot when emmc is not present (Pali) - DS414; config header cleanup (Phil) - PCI: auto-config enhancement (Phil) - pci_mvebu: Also map IO region (Phil) - serial: a3720: Implement pending method for output direction (Pali) - turris_mox: Enable a few commands (Marek) - helios4 & ClearFog changes (Dennis) - Plus some minor misc changes
| * ARM: mvebu: helios4 dts changes to enable SPIDennis Gilmore2021-01-272-11/+26
| | | | | | | | | | | | | | | | Move all aliases defintions into the main dts file Add u-boot definiton to i2c0 based on clearfog set spi1 status to okay Signed-off-by: Dennis Gilmore <dennis@ausil.us>
| * ARM: mvebu: helios4 adjust env sizes to enable SPI to workDennis Gilmore2021-01-271-0/+1
| | | | | | | | | | | | mirror the clearfog setup to enable SPI to work Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* | board: presidio-asic: Add CAxxxx Ethernet supportAlex Nemirovsky2021-01-271-0/+31
|/ | | | | | | | Add CAxxxx Ethernet support for the Cortina Access Presidio Engineering Board Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-01-2537-335/+4023
|\ | | | | | | | | | | | | | | - New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
| * sunxi: Add support for OrangePi Zero2Jernej Skrabec2021-01-252-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OrangePi Zero2 is SBC based on Allwinner H616 with 1 GiB of RAM, SD card support, gigabit ethernet, micro HDMI, WIFI, Bluetooth and 1 USB 2.0 port. It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken from v3 of the OrangePi Zero2 Linux submission [1], which it's not yet merged. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632084.html Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit (git 2.34.1) at 2025-09-30 22:48:08 +0000