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| * | | imx8mm_evk: Switch to new imx8mm evk boardYe Li2021-04-082-63/+68
| |/ / | | | | | | | | | | | | | | | Update PMIC to use PCA9540, the legacy board not supported by NXP Signed-off-by: Ye Li <ye.li@nxp.com>
* | | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-04-0810-36/+388
|\ \ \ | | | | | | | | | | | | - Watchdog, Unleashed and Icicle improvements
| * | | riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodesBin Meng2021-04-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The uart nodes already provide <clocks> property for the driver to dynamically calculate the correct clock frequency. There is no need to keep the hard-coded <clock-frequency> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
| * | | riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt2021-04-086-21/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * | | riscv: simplify longjmpHeinrich Schuchardt2021-04-081-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value returned by setjmp must be nonzero. If zero is passed as parameter it must be replaced by 1. This patch reduces the code size a bit. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * | | riscv: sifive: Rename fu540 board to unleashedBin Meng2021-04-082-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * | | riscv: Add watchdog bindings for the k210Sean Anderson2021-04-081-1/+0
| |/ / | | | | | | | | | | | | | | | | | | This adds the necessary bindings. Most of them are already there. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com>
* / / arm: kirkwood: remove non-dm MMC driver initHarm Berntsen2021-04-081-7/+0
|/ / | | | | | | | | | | | | | | | | | | No board uses this driver any more: remove it. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> Reviewed-by: Stefan Roese <sr@denx.de> CC: Gerald Kerma <drEagle@doukki.net> CC: Stefan Roese <sr@denx.de> CC: Pantelis Antoniou <panto@antoniou-consulting.com>
* | Merge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini2021-04-061-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | Update hwpartition usage Check bootbus's arguments workaround for erratum A-011334 for fsl_esdhc driver add pulse width detection workaround for fsl_esdhc driver Use alias num before checking mmc index when creating device
| * | mmc: fsl_esdhc: add pulse width detection workaroundMichael Walle2021-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: fsl_esdhc: add workaround for erratum A-011334Michael Walle2021-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | LS1028A SoCs are restricted in what divider values are allowed for HS400 mode. This is basically a port from the corresponding linux driver. Signed-off-by: Michael Walle <michael@walle.cc>
* | | Merge tag 'u-boot-amlogic-20210406' of ↵Tom Rini2021-04-067-238/+0
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic - Add MMIO MDIO mux driver - Add Amlogic G12A MDIO mux driver - Add DM_MDIO support for designware ethernet driver - Add Amlogic Meson8b and later designware ethernet glue driver - Switch all amlogic boards to Amlogic designware ethernet glue driver - Switch all amlogic boards to DM_MDIO when necessary - Remove all static ethernet setup code
| * | | arm: meson: remove static ethernet link setupNeil Armstrong2021-04-067-189/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The static ethernet link type config code is no more needed because now handled by the meson8b glue driver, delete it. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | arm: meson: remove static ethernet memory power domain enableNeil Armstrong2021-04-062-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ethernet memory power domain is handled by the meson-ee-pwrc driver, delete the static code. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | arm: meson: remove static MDIO mux handlingNeil Armstrong2021-04-062-45/+2
| |/ / | | | | | | | | | | | | | | | The static MDIO mux handling in mach-meson is no more needed, delete it. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | Merge tag 'rockchip-for-v2021.07' of ↵Tom Rini2021-04-0515-300/+963
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3368 lion board support; - Fix px30 odroid-go2 board support; - Add rk3399 NanoPi R4s and NanoPi M4B board support;
| * | board: dts: rockchip: Add NanoPi M4BAlexandre Vicenzi2021-03-303-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NanoPi M4B, a minor revision of the original NanoPi M4. Commit details of rk3399-nanopi-m4b.dts sync from Linux 5.12-rc4: "arm64: dts: rockchip: Add NanoPi M4B board" (sha1: c7b03115003f7f337ab165542cee37148cf30a8a) Signed-off-by: Alexandre Vicenzi <alexandre.vicenzi@suse.com> Reviewed-by: Kever Yang <kever.yang@rock-cihps.com>
| * | arm64: rk3399: Add support NanoPi R4sXiaobo Tian2021-03-303-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support, including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port. port.It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken of the rk3399 nanopi4 Linux kernel [1]. [1] https://github.com/torvalds/linux/commit/e7a095908227fb3ccc86d001d9e13c9ae2bef8e6 Signed-off-by: xiaobo <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399-puma: Restore correct VDD_LOG supply.Christoph Muellner2021-03-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A commit from last year re-imported the DTS files form the upstream kernel. By doing so the VDD_LOG regulator in the board's DTS was dropped. Let's restore this, but move it into the u-boot overlay to prevent this issue in the future. Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux") Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3368: sync down rk3368-lion board devicetree from LinuxHeiko Stuebner2021-03-304-68/+349
| | | | | | | | | | | | | | | | | | | | | | | | This brings the actual rk3368-lion devicetree files from Linux 5.10 instead of using something separate. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3368: sync main rk3368 dtsi from LinuxHeiko Stuebner2021-03-306-231/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the state as of v5.10 + the recently added timer0 phandle targetted at the 5.12 merge window. With this the non-mainline nodes like the dmc move to a separate rk3368-u-boot.dtsi that is included from the board-specific -u-boot.dtsi files, similar to how rk3399 does this. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3368: move STACK_R_ADDR address and into KconfigHeiko Stuebner2021-03-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the STACK_R_ADDR at 0x600000 (6MB) we're competing with with the loading address of either u-boot or atf parts, so move that away to 0x4000000 (64MB) similar to rk3399. Only lion currently sets that at all but not sheep the second rk3368 board, so just move that to the Kconfig for rk3368 similar to rk3399 as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000Heiko Stuebner2021-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | To prevent running out of memory, increase SYS_MALLOC_F_LEN to 0x4000 similar to what rk3399 uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge branch 'next'Tom Rini2021-04-05179-1191/+3468
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| * | Merge tag 'xilinx-for-v2021.07' of ↵Tom Rini2021-03-3122-258/+511
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
| | * | ARM: bitmain: Enable nand and smcc driversMichal Simek2021-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enable nand and smcc via DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | xilinx: Sync DTs with Linux kernelMichal Simek2021-03-3018-255/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Rename clocks as per the Arasan NAND driverAmit Kumar Mahapatra2021-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In zynqmp.dtsi file renamed "clk_sys" clock to "controller" and "clk_flash" clock to "bus" as per upstreamed Arasan NAND driver. This fixes NAND driver probe failure. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Update device tree properties for nand flashAmit Kumar Mahapatra2021-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the following device tree properties for nand flash - Set software ecc mode. - Set bch as ecc algo. - Set read block to 0. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Add idt 8a34001 chip to zcu208/zcu216Michal Simek2021-03-302-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | There is Linux driver for these chips that's why add it to device tree. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Add emmc specific parametersAshok Reddy Soma2021-03-302-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMMC will have bus-width 8 and it is non-removable in general. These are missing from dt node. Add bus-width and non-removable parameters to emmc node. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | Merge tag 'u-boot-atmel-2021.07-a' of ↵Tom Rini2021-03-302-8/+9
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.07 cycle: This small feature set includes the implementation of the slew rate for the PIO4 pin controller device, and a fix for arm926ejs-based microprocessors that avoids a crash.
| | * | | ARM: mach-at91: arm926ejs: fix data abort in startup returning from ↵Martin Townsend2021-03-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init The startup code in arm/cpu/arm926ejs preserves the link register across the call to lowlevel_init by using r4: mov r4, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, r4 /* restore link */ The lowlevel_init function for at91 machines based on the same CPU uses r4 and hence corrupts it causing a data abort when it returns to the startup code. This patch fixes this by using r6 instead of r4 in the lowlevel_init function. Discovered and the fix was tested on a AT91SAM9261 based board. Signed-off-by: Martin Townsend <martin@rufilla.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
| | * | | pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea2021-03-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAMA7G5 supports slew rate configuration. Adapt the driver for this. For switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | | Merge tag 'v2021.04-rc5' into nextTom Rini2021-03-292-1/+10
| |\ \ \ \ | | | |/ / | | |/| / | | |_|/ | |/| | Prepare v2021.04-rc5
| * | | sandbox: define __dyn_sym_start, dyn_sym_endHeinrich Schuchardt2021-03-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On RISC-V the symbols __dyn_sym_start, dyn_sym_end are referenced in efi_runtime_relocate(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: coral: Show memory config and SKU ID on startupSimon Glass2021-03-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide the model information through sysinfo so that it shows up on boot. For memconfig 4 pins are provided, for 16 combinations. For SKU ID there are two options: - two pins provided in a ternary arrangement, for 9 combinations. - reading from the EC Add a binding doc and drop the unused #defines as well. Example: U-Boot 2021.01-rc5 CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz DRAM: 3.9 GiB MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 Video: 1024x768x32 @ b0000000 Model: Google Coral (memconfig 5, SKU 3) This depends on the GPIO series: http://patchwork.ozlabs.org/project/uboot/list/?series=228126 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
| * | | sandbox: Correct uninit conflictSimon Glass2021-03-271-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not possible to remove the state before driver model is uninited, since the devices are allocated in the memory buffer. Also it is not possible to uninit driver model afterwards, since the RAM has been freed. Drop the uninit altogether, since it is not actually necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-274-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Only delete the executable if requestedSimon Glass2021-03-271-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox removes its executable after failing to run it, since there is no other way that it would get cleaned up. However, this is actually only wanted if the image was created within sandbox. For the case where the image was generated by the build system, such as u-boot-spl, we don't want to delete it. Handle the two code paths accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coreboot: Don't setup MTRR when booting from corebootSimon Glass2021-03-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This currently hangs and it is not necessary in any case. Drop the code when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: fsp: Don't notify if booted from corebootSimon Glass2021-03-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from coreboot there is no need to notify the FSP of anything, since coreboot has already done it. Nor it is possible, since the FSP details are not provided by coreboot. Skip it in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coral: Fall back to coreboot video when FSP missingSimon Glass2021-03-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from coreboot the FSP video information is no-longer available. Enable the coreboot driver so that we can get some sort of display in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coral: Allow init of debug UART in U-Boot properSimon Glass2021-03-274-58/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coral: Avoid build error with !CONFIG_ACPIGENSimon Glass2021-03-271-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this by moving things around. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: fsp: Don't enable FSP graphics if booted from corebootSimon Glass2021-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver cannot work when booted from coreboot, since the FSP information is not available. Disable it in that case, so that the coreboot video driver can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: Allow installing an e820 when booting from corebootSimon Glass2021-03-275-29/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coreboot: Update parsing of the latest sysinfoSimon Glass2021-03-273-57/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass2021-03-275-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: coreboot: Sync up timestamp codesSimon Glass2021-03-272-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-30 08:45:24 +0000